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  • हिन्दी Eng

    • Dr. Dipjyoti Das

    Dr.Dipjyoti Das

    Information

    • Designation : Assistant Professor
    • Email : dipjyoti@ece.nits.ac.in
    • Phone : 9864865210

    Key Notes

    • Conference: International - 12
    • Journals: 37
    • Conferences: 12
    • Book Chapter: 1
    • Patents: 2
    • Post Graduates: Guided: 4

    50

    PUBLICATIONS

    2

    PATENTS

    Introduction [Biosketch]

    • Dr. Dipjyoti Das is an accomplished academician and researcher specializing in semiconductor devices, microelectronics, and ferroelectric materials. He holds a Ph.D. from the Indian Institute of Technology (IIT) Guwahati and has enriched his expertise through postdoctoral research at globally renowned institutions, including the Georgia Institute of Technology (USA) and the Korea Advanced Institute of Science and Technology (KAIST, South Korea). Currently, he serves as an Assistant Professor at NIT Silchar.
    • His work has been published in top-tier journals such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, and ACS Applied Materials & Interfaces, with over 1,200 citations (h-index: 20). His publications include 37 peer-reviewed journal articles, 11 conference papers, and a book chapter.

    Areas of Interest

    • Ferroelectronics, Semiconductor Devices, Nanoelectronics, Organic Optoelectronic Devices, Non-volatile Memory

    Institution Year Degree
    Indian Institute of Technology, Guwahati 2018 PhD
    Assam Engineering College 2011 Bachelor of Engineering

    Teaching Experience
    Assistant Professor
    28 December 2023 - Present
    National Institute of Technology, Silchar
    Industrial/Research Experience
    Postdoctoral Fellow / Electrical and Computer Engineering
    Georgia Institute of Technology, Atlanta, USA
    Post-doctoral Researcher / Electrical Engineering
    Korea Advanced Institute of Science and Technology, South Korea

    P. V. Ravindran, C. Park, T. Song, L. Fernandes, D. Das, N. Afroze, P. G. Ravikumar, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Mahapatra, S. Yu, S. Datta, A. Khan, “Disturb and its mitigation in ferroelectric field effect transistors with large memory window for NAND Flash applications”, IEEE ELECTRON DEVICE LETTERS, Volume 45, Issue 12, 2367 - 2370, December, 2024, 10.1109/LED.2024.3467210, Indexed in SCIE, Impact Factor: 4.1, Quartile: Q2

    L. Fernandes, P. V. Ravindran, T. Song, D. Das, C. Park, N. Afroze, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, A. Khan, “Material choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications”, IEEE ELECTRON DEVICE LETTERS, Volume 45, Issue 10, 1776 - 1779, October, 2024, 10.1109/LED.2024.3437239, Indexed in SCIE, Impact Factor: 4.1, Quartile: Q2

    C. Park, P. V. Ravindran, D. Das, P. G. Ravikumar, C. Zhang, N. Afroze, L. Fernandes, Y. H. Kuo, J. Hur, H. Chen, M. Tian, W. Chern, S. Yu, A. I. Khan, “Plasma-Enhanced Atomic Layer Deposition-Based Ferroelectric Field-Effect Transistors”, IEEE Journal of the Electron Devices Society, Volume 12, 569-572, 2024, Indexed in SCIE, Impact Factor: 2, Quartile: Q2

    M. Passlack, N. Tasneem, C. Park, P. Ravindran, H. Chen, D. Das, S. Yu, E.Chen, J.-F Wang, C-S. Chang, Y-M. Lin, I. Radu, A. Khan, “The origin of memory window closure with bipolar stress cycling in silicon ferroelectric field-effect-transistors”, JOURNAL OF APPLIED PHYSICS, Volume 135, Issue 13, 2024, Indexed in SCIE, Impact Factor: 2.7, Quartile: Q2

    Rajib Sutradhar, Chinmaya Kumar Pradhan, Himangshu Jyoti Gogoi, Pukhrambam Puspa Devi, Kuldeep Gogoi, Dipjyoti Das, “Material Characterization and Resistive Switching Properties of Lead-Free Cs2CuBiCl6 for Memory Applications”, In Proceedings 5th International Conference on Micro and Nanoelectronics Devices, Circuits and Systems, 2025, January 31st 2025, 2025, National Institute of Technology Silchar, India, Springer, Indexed in Scopus, Ranking Best Paper Award

    Sl.No Course Name Semester Course Code Duration Status
    1 Power Electronics B.Tech EC 310
    2 Electrical and Electronics Materials B.Tech EC 208
    3 Selected Topic on VLSI B.Tech EC 485
    4 Basic Electronics B.Tech EC 101

    ReRAM, Double Perovskite

    Rajib Sutradhar
    Enrolled: 25 August 2023
    Ongoing
    Supervisor : Pukhrambam Puspa Devi
    Co Supervisor : Dipjyoti Das

    Novel Gate Stack Design for Fe-NAND

    Abhiyant Singh
    Enrolled: 6 August 2024
    Ongoing
    Supervisor : Dipjyoti Das

    Charge Trapping Effects, Ferroelectric Memories

    Aman Kumar
    Enrolled: 22 August 2024
    Ongoing
    Supervisor : Dipjyoti Das

    Kottana Jagadeesh
    Enrolled: 12 August 2024
    Ongoing
    Supervisor : Srimanta Baishya
    Co Supervisor : Dipjyoti Das

    Awards And Honours

      • 2024 Haedong best paper award (academic category) 2024
      • BK21+ Fellowship, South Korea. 2019 – 2020
      • Senior Research Fellow, MHRD, Govt, of India. 2014 – 2017
      • Junior Research Fellow, MHRD, Govt, of India. 2012 – 2014
      • Certificate of Proficiency, Assam Higher Secondary Education Council, Assam. 2007
      • Anundoram Borooah Award 2005, Govt. of Assam. 2005

    FERROELECTRIC GATE STACK WITH TUNNEL DIELECTRIC INSERT FOR NAND APPLICATIONS

    “A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”

    USA
    Patent Registration ID, 63/606,684
    FERROELECTRIC GATE STACK WITH TUNNEL DIELECTRIC INSERT FOR NAND APPLICATIONS, (**GRANTED**)

    DISTURB MITIGATION SCHEME FOR FERROELECTRIC FIELD-EFFECT TRANSISTORS

    “A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”

    USA
    Patent Registration ID, 63/692,275
    DISTURB MITIGATION SCHEME FOR FERROELECTRIC FIELD-EFFECT TRANSISTORS, (**GRANTED**)

    Sl.No Award/Recognition/Achievement Year Approved agency
    1 Haedong Best Paper Award (Academic Category) 2024 The Institute of Electronics and Information Engineers
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