Information
- Designation : Assistant Professor
- Email : kavicharan@ece.nits.ac.in
- Phone : 8919656540
Key Notes
- Conference: International - 28
- Journals: 33
- Conferences: 28
- Book Chapters: 10
- Book: 1
- Patents: 3
- PhD: Guided: 3
72
PUBLICATIONS3
DOCTORAL STUDENTS3
PATENTS1
PROJECTIntroduction [Biosketch]
- Dr. M. Kavicharan received B.Tech degree in Electronics and Communication Engineering Department from JNTU Hyderabad in 2006. The M.Tech degree in Electrincs Design and Technology from NIT Calicut in 2009 and Ph.D from NIT Warangal in 2015. His research interests include: VLSI interconnects, Signal Integrity, Power Integrity, Device Modelling, Carbon Nanotube Interconnects. He is a member of IEEE Electron devices society. He is a IEEE Senior member and Fellow of IETE India.
Areas of Interest
- VLSI, Signal Integrity, Power Integrity, Semiconductor Device Modelling and Simulation, Stretchable electronics.
| Institution | Year | Degree |
|---|---|---|
| NIT Warangal, Telangana | 2015 | Ph.D. (Engg.) |
| NIT Calicut, Kerala | 2009 | M.Tech. |
| JNTU Hyderabad, Telangana | 2006 | B.Tech. |
Teaching Experience
National Institute of Technology Silchar
Thapar University, Patiala, Punjab
MREC(A), Hyderabad
P Kumar, JK Ratan, N Divya, K Mummaneni, G Rawat, “Investigation of CeO₂/rGO Nanocomposites as Diesel Additives to Enhance Engine Performance and Reduce Exhaust Emissions”, In Proceedings IEEE 9th International Conference on Signal Processing and Communication (ICSC), 2023
Malvika, J. Talukdar, B. Choudhuri, G.Rawat, K. Mummaneni, “Exploration of Graphene as Emerging 2D Material and its Applications: A Review”, In Proceedings COMSYS 2023, 2023
Venkatasatyakranthikumar, T., Dey, S., Malvika, kumar, V. and Mummaneni, K., “Design and Implementation of Bus Ticketing System Using Verilog HDL”, In Proceedings 3rd International Conference on Micro/Nanoelectronics Devices, Circuits and Systems, 2023
Halder, S., Saha, M.L., Malvika, Talukdar, J. and Mummaneni, K.,, “Design and Implementation of an Optimized High-Speed Vedic-Based Squarer Circuit Using Reversible Logic Gates”, In Proceedings 3rd International Conference on Micro/Nanoelectronics Devices, Circuits and Systems, 2023
Kavicharan Mummaneni, Vivek Kumar, Malvika, Yash Agrawal, “Delay Analysis of Different Stretchable Interconnect Structures”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Gulafsha Bhatti, Yash Agrawal, Vinay Palaparthy, Kavicharan Mummaneni, Meenu Agrawal, “Flexible Electronics: A Critical Review”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Gulafsha Bhatti, Yash Agrawal, Vinay Palaparthy, Kavicharan Mummaneni, Meenu Agrawal, “Flexible Electronics: A Critical Review”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Vivek Kumar, Malvika, Yash Agrawal, Kavicharan Mummaneni, “Stretchable Interconnects: Materials, Geometry, Fabrication and Applications”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics,, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
P. Uma Sathyakam, P. S. Mallick, Kavicharan Mummaneni, “Triangular CNT bundle interconnects for next generation integrated circuits”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Kavicharan Mummaneni, Vivek Kumar, Malvika, P. Uma Sathyakam, “Modelling and Analysis of Copper and Carbon Nanotube VLSI Interconnects”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Yash Agrawal, Vinay Palaparthy, Mekala Girish Kumar, Kavicharan Mummaneni, Rajeevan Chandel, “Explicit Power-Delay Models for On-chip Copper and SWCNT Bundle Interconnects”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Malvika, Vivek Kumar, Kavicharan Mummaneni, “Delay and Overshoot Modelling of Asymmetric T-Tree Interconnects”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Kavicharan Mummaneni, Malvika, Vivek Kumar, “An Efficient Model Order Reduction of Interconnects using Machine Learning for Timing Analysis”, Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics, 2023, Springer Book: Tracts in Electrical and Electronics Engineering
Malvika, Bijit choudhuri, Kavicharan Mummaneni, “Basic Operation Principle of Negative Capacitance Field Effect Transistor”, Negative Capacitance Field Effect Transistors, 2023, Taylor and Francis group, CRC Press
Agrawal, Y., Mummaneni, K., Sathyakam, P.U., Agrawal, Y., Mummaneni, K., Sathyakam, P.U., “Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics”, 2023, , Springer Book: Tracts in Electrical and Electronics Engineering
TFET
Jagritee Talukdar
Completed :
Supervisor : Dr. Kavicharan Mummaneni
NCFET
Malvika
Completed :
Supervisor : Dr. Kavicharan Mummaneni
Co Supervisor : Dr. Bijit Choudhuri
NCFET
Vivek Kumar
Supervisor : Dr. Kavicharan Mummaneni
3-DIMENSIONAL CYLINDRICAL FERROELECTRIC BASED NEGATIVE CAPACITANCE GATE-ALL-AROUND FET SILICON-NANOWIRE DEVICE FOR LOW POWER APPLICATIONS
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
South Africa
Patent
Registration ID, 2024/05816
3-DIMENSIONAL CYLINDRICAL FERROELECTRIC BASED NEGATIVE CAPACITANCE GATE-ALL-AROUND FET SILICON-NANOWIRE DEVICE FOR LOW POWER APPLICATIONS, (**GRANTED**)
A GATE UNDERLAP LIGHTLY-DOPED DRAIN AND RAISED DRAIN NEGATIVE-CAPACITANCE FIELD-EFFECT TRANSISTOR DEVICE AND ITS FABRICATION METHOD THEREOF
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
INDIA
Patent
Registration ID, 2024-31063984
A GATE UNDERLAP LIGHTLY-DOPED DRAIN AND RAISED DRAIN NEGATIVE-CAPACITANCE FIELD-EFFECT TRANSISTOR DEVICE AND ITS FABRICATION METHOD THEREOF, (**GRANTED**)
MINIATURE QUARTER MODE SUBSTRATE INTEGRATED WAVEGUIDE FILTER FOR RADIO FREQUENCY COMMUNICATION
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
India
Patent
Registration ID, 410117-001
MINIATURE QUARTER MODE SUBSTRATE INTEGRATED WAVEGUIDE FILTER FOR RADIO FREQUENCY COMMUNICATION, (**GRANTED**)
Sl.No: 1
Title Of Research Project: " Development of Low Cost Early Warning System for Detection of Earthquake Induced Landslide "
Sponsored By:
Overall Budget: Rs 4900000
| Sl.No | Award/Recognition/Achievement | Year | Approved agency |
|---|---|---|---|
| 1 | Senior Member, IEEE | IEEE |
| Sl.No | Course Title | Resource Person | Documents | Area | Funding Agency | Date |
|---|---|---|---|---|---|---|
| 1 | Faculty development program | Mixed Signal Design & Verification using Cadence Tools | Feb 27 2015 | |||
| 2 | Faculty development program | Emerging trends in Analog and Digital design using Cadence: Hands on Learning | Jun 06 2016 | |||
| 3 | Workshop | Modeling of Novel Nano electronic Devices and Circuits for ULSI Technology | DST-SERB and TEQIP-III sponsored | Apr 26 2019 | ||
| 4 | Workshop | Recent Trends in Innovative CMOS-MEMS Technologies and Applications: Hands on Learning | TEQIP-III Sponsored | Sep 11 2020 | ||
| 5 | Workshop | Prototype/Process Design and Development | Feb 14 2022 |
