Information
- Designation : Assistant Professor
- Email : kavicharan@ece.nits.ac.in
- Phone : 8919656541
Key Notes
- Conference: International - 32 , National - 2
- Journals: 43
- Conferences: 38
- Book Chapters: 12
- Book: 1
- Patents: 3
- PhD: Guided: 4
94
PUBLICATIONS4
DOCTORAL STUDENTS3
PATENTS2
PROJECTSIntroduction [Biosketch]
- Dr. M. Kavicharan received B.Tech degree in Electronics and Communication Engineering Department from JNTU Hyderabad in 2006. The M.Tech degree in Electrincs Design and Technology from NIT Calicut in 2009 and Ph.D from NIT Warangal in 2015. His research interests include: VLSI interconnects, Signal Integrity, Power Integrity, Device Modelling, Carbon Nanotube Interconnects. He is a member of IEEE Electron devices society. He is a IEEE Senior member and Fellow of IETE India.
Areas of Interest
- VLSI, Signal Integrity, Power Integrity, Semiconductor Device Modelling and Simulation, Stretchable electronics.
| Institution | Year | Degree |
|---|---|---|
| NIT Warangal, Telangana | 2015 | Ph.D. (Engg.) |
| NIT Calicut, Kerala | 2009 | M.Tech. |
| JNTU Hyderabad, Telangana | 2006 | B.Tech. |
Teaching Experience
National Institute of Technology Silchar
National Institute of Technology Silchar
Thapar University, Patiala, Punjab
MREC(A), Hyderabad
Kavicharan Mummaneni, “Analytical Modeling of Gate-All-Around Negative Capacitance Field Effect Transistor using Drain Current Model”, In Proceedings International Conference on Automation for Sustainable Future 2.0,, February 27th 2026 - February 28th 2026, 2026
P. S. Ganaraj, K. Guha, and K. Mummaneni, “Design of a compact dual-band quarter-mode SIW filter for Ku- and Ka-band applications”, In Proceedings IEEE Proc. Microwaves, Antennas, and Propagation Conf. (MAPCON),, December 14th 2025 - December 18th 2025, 2025
Y. Anusha, K. Guha, and K. Mummaneni, “Design and analysis of a novel RF MEMS switch for smart sensors and IoT applications”, In Proceedings IEEE Proc. Microwaves, Antennas, and Propagation Conf. (MAPCON),, December 14th 2025 - December 18th 2025, 2025
Talukdar, J., Malvika, , Das, B. and Mummaneni, K., “Tunnel Field Effect Transistors.”, In Handbook of Advanced Semiconductor Field Effect Transistorss, 2025
Agrawal, Y., Mummaneni, K., Sathyakam, P.U., Agrawal, Y., Mummaneni, K., Sathyakam, P.U., “Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics”, 2023, , Springer Book: Tracts in Electrical and Electronics Engineering
Design and Development of Under Water Acoustic Wireless Sensor Networks
Kadali Lakshmi
Supervisor : Kavicharan Mummaneni
Modelling, Simulation and Applications of Highly Doped Double Pocket Double Gate Negative Capacitance Field Effect Transistor (HDDP-DG-NCFET)
Malvika
Completed :
15 November 2025
Supervisor : Dr. Kavicharan Mummaneni
Co Supervisor : Dr. Bijit Choudhuri
Analytical Modeling and Analysis of the Ferroelectric Parameter Variability in the Electrical, Noise, and Thermal behavior of NC-GAAFET Nanowire for Ultra-Low Power Applications
Vivek Kumar
Supervisor : Dr. Kavicharan Mummaneni
Simulation, Modelling and Applications of Source Engineered Asymmetric Tunnel FET
Jagritee Talukdar
Completed :
4 November 2022
Supervisor : Dr. Kavicharan Mummaneni
3-DIMENSIONAL CYLINDRICAL FERROELECTRIC BASED NEGATIVE CAPACITANCE GATE-ALL-AROUND FET SILICON-NANOWIRE DEVICE FOR LOW POWER APPLICATIONS
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
South Africa
Patent
Registration ID, 2024/05816
3-DIMENSIONAL CYLINDRICAL FERROELECTRIC BASED NEGATIVE CAPACITANCE GATE-ALL-AROUND FET SILICON-NANOWIRE DEVICE FOR LOW POWER APPLICATIONS, (**GRANTED**)
A GATE UNDERLAP LIGHTLY-DOPED DRAIN AND RAISED DRAIN NEGATIVE-CAPACITANCE FIELD-EFFECT TRANSISTOR DEVICE AND ITS FABRICATION METHOD THEREOF
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
INDIA
Patent
Registration ID, 2024-31063984
A GATE UNDERLAP LIGHTLY-DOPED DRAIN AND RAISED DRAIN NEGATIVE-CAPACITANCE FIELD-EFFECT TRANSISTOR DEVICE AND ITS FABRICATION METHOD THEREOF, (**GRANTED**)
MINIATURE QUARTER MODE SUBSTRATE INTEGRATED WAVEGUIDE FILTER FOR RADIO FREQUENCY COMMUNICATION
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
India
Patent
Registration ID, 410117-001
MINIATURE QUARTER MODE SUBSTRATE INTEGRATED WAVEGUIDE FILTER FOR RADIO FREQUENCY COMMUNICATION, (**GRANTED**)
Sl.No: 1
Title Of Research Project: " Development of Low Cost Early Warning System for Detection of Earthquake Induced Landslide "
Sponsored By:
Overall Budget: Rs 4900000
Sl.No: 2
Title Of Research Project: " FIST "
Sponsored By: DST
Overall Budget: Rs 12800000
Status: Ongoing
Co Principal Investigator: Dr. Kavicharan Mummaneni
| Sl.No | Award/Recognition/Achievement | Year | Approved agency |
|---|---|---|---|
| 1 | Senior Member, IEEE | IEEE |
| Sl.No | Course Title | Resource Person | Documents | Area | Funding Agency | Date |
|---|---|---|---|---|---|---|
| 1 | Faculty development program | Mixed Signal Design & Verification using Cadence Tools | Feb 27 2015 | |||
| 2 | Faculty development program | Emerging trends in Analog and Digital design using Cadence: Hands on Learning | Jun 06 2016 | |||
| 3 | Workshop | Modeling of Novel Nano electronic Devices and Circuits for ULSI Technology | DST-SERB and TEQIP-III sponsored | Apr 26 2019 | ||
| 4 | Workshop | Recent Trends in Innovative CMOS-MEMS Technologies and Applications: Hands on Learning | TEQIP-III Sponsored | Sep 11 2020 | ||
| 5 | Workshop | Prototype/Process Design and Development | Feb 14 2022 |
