Information
- Designation : Professor
- Email : klb@ece.nits.ac.in
- Phone : 9435176506
Key Notes
- Conference: International - 31
- Journals: 68
- Conferences: 37
- Book Chapters: 8
- Patents: 3
- PhD: Guided: 15
113
PUBLICATIONS15
DOCTORAL STUDENTS3
PATENTS3
PROJECTSIntroduction [Biosketch]
- Dr. K. L. Baishnab is a Professor in the Department of Electronics and Communication Engineering at the National Institute of Technology. He joined the institute on 17th March 1998 as a Lecturer in the same department. Prior to joining REC Silchar, Dr. Baishnab worked for about two years as an Engineer at Widecom Fax and Plotter Ltd., NOIDA.
- He obtained his Bachelor’s degree in Electronics and Telecommunication Engineering from Regional Engineering College (REC) Silchar, followed by a Master’s degree in Electronics and Telecommunication Engineering from the Indian Institute of Technology (IIT) Kharagpur. He received his PhD in Analog/Mixed-Mode VLSI Circuits for Visual Processing.
- With over 27+ years of teaching and research experience, Dr. Baishnab has been actively engaged in both VLSI Design and Communication Engineering. He has delivered numerous expert lectures on VLSI circuit design for biomedical signal processing. He has several SCI-indexed journal publications and book chapters published by reputed publishers such as Springer, Elsevier, Taylor & Francis, among others.
- To date, 15 of his PhD scholars have been awarded the PhD degree
Areas of Interest
- Analog and RF VLSI Circuit Design, Algorithm to VLSI Architecture, Cryptography, Cloud Computing
| Institution | Year | Degree |
|---|---|---|
| PhD in Analog/Mixed VLSI for Visual Computation, VLSI Design for Machine Learning, Cryptography, Machine learning for Medical science etc | Doctor of Philosophy |
M Preeti, Koushik Guha, KL Baishnab, Jacopo Iannacci, Massimo Donelli, Narayan Krishnaswamy, “Analysis of a low frequency MEMS capacitive accelerometer under the effect of biasing voltage for detection of Parkinsons tremor”, Microsystem Technologies, Volume 31, Issue 2, February, 2025, Indexed in SCIE, Impact Factor: 1.8
Lokenath Kundu, Subhanil Maity, Sourav Nath, Gaurav Singh Baghel, Krishna Lal Baishnab, “[PDF] from ieee.org A Design Approach for ZigBee Compatible CML-based 2/3 Dual Modulus Frequency Divider”, In Proceedings 2024 28th International Symposium on VLSI Design and Test (VDAT), September 1st 2024 - September 3rd 2024, 2024, Vellore, India, IEEE, 1-6
Sourav Nath, Lokenath Kundu, Koushik Guha, KL Baishnab, “Design and Analysis of Cross-Coupled Source Degenerated Balanced OTA for Biomedical Application”, In Proceedings 2024 28th International Symposium on VLSI Design and Test (VDAT), September 1st 2024 - September 3rd 2024, 2024, Vellore, India, IEEE, 1-6
Analog VLSI Circuit Design
Lokenath Kundu
Enrolled: 11 August 2020
Completed :
16 June 2025
Supervisor : Prof. Krishna Lal Baishnab
Co Supervisor : Dr. G.S. Baghel
Academic Year : 2025-2026
Semiconductor Device
Neeraj Kumar Niranjan
Enrolled: 26 June 2018
Completed :
15 November 2024
Supervisor : Prof. Madhuchhanda Choudhury
Co Supervisor : Prof. K.L. Baishnab
MEMS
Preeti Mallela
Enrolled: 24 July 2017
Completed :
28 October 2024
Supervisor : Dr. Koushik Guha
Co Supervisor : Prof. K.L. Baishnab
Academic Year : 2024-2025
Analog VLSI Circuit Design
Sourav Nath
Enrolled: 12 August 2020
Completed :
4 October 2024
Supervisor : Prof. K.L. Baishnab
Co Supervisor : Dr. Koushik Guha
Academic Year : 2024-2025
Cryptography
Siddhartha Roy
Enrolled: 24 July 2018
Completed :
17 November 2022
Supervisor : Prof. K.L. Baishnab
Academic Year : 2022-2023
VLSI Physical Design
Naorem Yaipharenba Meitei
Enrolled: 27 July 2015
Completed :
21 July 2022
Supervisor : Prof. K.L Baishnab
Co Supervisor : Dr. Gaurav Trivedi
Academic Year : 2022-2023
Communication
Arifa Ahmed
Enrolled: 28 July 2015
Completed :
9 June 2022
Supervisor : Prof. K.L. Baishnab
Co Supervisor : Dr. Ganesh Prasad
Academic Year : 2022-2023
Semiconductor Device
Sagarika Choudhury
Enrolled: 24 July 2018
Completed :
25 March 2022
Supervisor : Prof. K.L. Baishnab
Analog Circuit Design and Optimization
Naushad Manzoor Laskar
Enrolled: 14 February 2017
Completed :
3 May 2021
Supervisor : Dr. Koushik Guja
Co Supervisor : Prof. K.L. Baishnab
Academic Year : 2021-2022
Cryptography
Arpita Biswas
Enrolled: 26 August 2016
Supervisor : Prof. K.L. Baishnab
Academic Year : 2020-2021
Nanotechnology
PARAMITA SARKAR
Enrolled: 3 August 2015
Completed :
11 February 2021
Supervisor : Prof. K.L. Baishnab
Co Supervisor : Dr. S.K. Tripathy
Academic Year : 2021-2022
Optimisation
Chabungbam Lison Singh
Enrolled: 11 July 2014
Completed :
15 June 2020
Supervisor : Prof. K.L. Baishnab
Academic Year : 2020-2021
Cloud Computing
ABHISHEK MAJUMDAR
Enrolled: 28 July 2015
Completed :
14 December 2019
Supervisor : Prof. K.L. Baishnab
Co Supervisor : Dr. S.K. Sood
Academic Year : 2019-2020
Communication
Ashim Gogoi
Enrolled: 10 July 2014
Completed :
14 June 2019
Supervisor : Prof. K.L. Baishnab
Academic Year : 2019-2020
Optimisation
Prashanta Kumar Paul
Completed :
5 September 2016
Supervisor : Prof. K.L. Baishnab
Academic Year : 2016-2017
Awards And Honours
- # Best paper in VLSI Design Conference 6th --7th January 2016" Applying River Formation Dynamics to Analyze VLSI Power Grid Networks " at Kolkata
- # Among Top 5 in prestigious CADENCE DESIGN CONTEST 2012 and 2011 for B.Tech and M.Tech Category respectively
A System For Developing A Lightweight Block Cipher For Resource Restricted Applications
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
Germany
Patent
Registration ID, H04L9/06
A System For Developing A Lightweight Block Cipher For Resource Restricted Applications, (**GRANTED**)
Novel Si0.8Ge0.2 source dual gate pocket 2-D TFET based breast-cancer cell lines detection
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
Gemany
Patent
Registration ID, H01L29/78
Novel Si0.8Ge0.2 source dual gate pocket 2-D TFET based breast-cancer cell lines detection, (**GRANTED**)
Spike: An ultra-fast, ultrasmall, ultra-low power robust block cipher for resource constrained IOT security applications.
“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”
German
Patent
Registration ID, DE202021105811U1
Spike: An ultra-fast, ultrasmall, ultra-low power robust block cipher for resource constrained IOT security applications., (**GRANTED**)
Sl.No: 1
Title Of Research Project: " Special Manpower Development Programme for Chips to System Design (SMDP-C2SD) (Currently undergoing)Special Manpower Development Programme for Chips to System Design (SMDP-C2SD) (Currently undergoing) "
Sponsored By: MeitY
Overall Budget: Rs 16000000
Duration: Dec 15, 2014 - Nov 30, 2021 (6 years 11 months 22 days)
Status: Completed
Principal Investigator: Prof. K.L.baishnab
Co Principal Investigator: Dr. Koushik Guha
Sl.No: 2
Title Of Research Project: " Design and Development of Low Power Low Latency Non-Invasive Seizer Detector System "
Sponsored By: MeitY
Overall Budget: Rs 10989000
Duration: Aug 23, 2023 - Feb 10, 2027 (3 years 5 months 18 days)
Principal Investigator: Prof. K.L. Baishnab
Co Principal Investigator: Dr. Koushik Guha
Sl.No: 3
Title Of Research Project: " Design and Modeling of Lab-On-Chip based Bio-reactors Capable of Mimicking Human Glomerulus Ultrafiltration and Reabsorption Function of Proximal Tubule of Kidney for in vivo implantation "
Sponsored By: DST
Overall Budget: Rs 26.44
Principal Investigator: Dr Koushik Guha
Co Principal Investigator: Prof Krishna Lal Baishnab
| Sl.No | Award/Recognition/Achievement | Year | Approved agency |
|---|---|---|---|
| 1 | An indigenously designed bio-sensor semiconductor chip for electroencephalogram (EEG) signal detection has been successfully conceptualized and developed at the VLSI Laboratory of the National Institute of Technology Silchar Assam India | 2025 | SCL Mahali Fabrication Centre |
