Prof. Srimanta Baishya

February 28, 2022 by Srimanta Baishya
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picnic photo_04-05-19-18-46-30

Professor

National Institute of Technology (NIT) Silchar

Department of Electronics and Communications Engineering

Silchar, Assam, 788010, India

Email: sb@ece.nits.ac.in

 

Date of Joining: 05/04/1991

Academic Experience: 33+ years

Personal Webpage: http://ec.nits.ac.in/sb/

ACADEMIC QUALIFICATIONS

  • Ph.D.: Jadavpur University, Kolkata, India
  • M.Tech.: Electrical Engineering, Indian Institute of Technology (IIT) Kanpur, India
  • BE (Hons): Electrical Engineering, Assam Engineering College, Assam, India

EXPERIENCE

  • Jul 2008 – Present: Professor, National Institute of Technology (NIT), Silchar, Assam, 788010, India
  • Jan 2006 – Jul 2008: Associate Professor, National Institute of Technology (NIT), Silchar, Assam, 788010, India
  • Mar 1999 – Dec 2006: Assistant Professor, National Institute of Technology (NIT), Silchar, Assam, 788010, India
  • Apr 1991 – Mar 1998: Lecturer

RESEARCH INTERESTS AND SPECIALIZATION

  • Solid State Device Modeling and Simulation
  • Electronic Circuits
  • VLSI
  • MEMS

BIOGRAPHICAL SKETCH

S. Baishya received the B.E. degree in electrical engineering from Assam Engineering College, Guwahati, India, the M.Tech. degree in electrical engineering from the Indian Institute of Technology (IIT), Kanpur, India, and Ph.D. degree in the field of MOS Modeling from Jadavpur University, Kolkata, India, respectively. Currently, he is a Professor in Electronics and Communication Engineering of NIT Silchar, India. His current research interests include the MOS physics and modeling, and MEMS.

PROJECT(S)

  1. Subthreshold Modeling and Simulation of FINFETs, AICTE
  2. MEMS Design Center under NPMASS
  3. Development of National Disaster Spectrum (NDS) and Disaster Communication Backbone Architecture (DiCoBA) with Prototype Development, in collaboration with IIT Kharagpur, DeitY
  4. Hetero-Junction Tunnel FETs: Characterization, Modeling, and Simulation of Electrical Parameters, Rs. 8,82,667, NCERT

PUBLICATION (JOURNALS/CONFERENCES)

Journals

  1. Pragati Singh, R. S. Dhar, and S. Baishya, “Micro-features of Ambipolar Snapback Behaviour under High Current injection to design capacitorless memory device,” Physica Scripta, vol. 96, no. 12, pp. 124069, December, 2021. DOI: https://doi.org/10.1088/1402-4896/ac3b69
  2. Kuheli Roy Barman and S. Baishya, “Structural Optimization of a Junctionless VSTB FET to Improve its Electrical and Thermal Performance”, IEEE Transactions on Nanotechnology, vol. 20, pp: 818-825, october, 2021. DOI: 10.1109/TNANO.2021.3119025
  3. Rajesh Saha, Rupam Goswami, and S. Baishya, “Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET),” Silicon, vol. 14, pp. , September, 2021. DOI: https://doi.org/10.1007/s12633-021-01365-0
  4. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Dependence of Lateral Straggle Parameter on DC, RF/Analog, and Linearity Performance in SOI FinFET,” IETE Journal of Research, vol. pp. , September, 2021. DOI: https://doi.org/10.1080/03772063.2021.1973915
  5. Kuheli Roy Barman and S. Baishya, “Improved Electrical and RF Performance of a Junctionless Vertical Super-Thin Body (VSTB) FET by Increased Substrate Doping,” Material Science in Semiconductor Processing, vol. 135, pp. 106100, November, 2021. DOI: https://doi.org/10.1016/j.mssp.2021.106100
  6. Pragati Singh, Rudra Sankar Dhar, and S. Baishya, “Physics & Modeling of Ambipolar Snapback Behavior in Gate Grounded NMOS,” Silicon, April, 2021 DOI: https://doi.org/10.1007/s12633-021-01086-4
  7. Moumita Pal, N. P. Maity, S. Baishya, and Reshmi Maity, “Performance Analysis of Nano-Electro-Mechanical-System Ultrasonic Sensor with Fringing Field Effects,” Trans. On Electrical and Electronic Materials, March, 2021. DOI: https://doi.org/10.1007/s42341-021-00297-1
  8. Rajashree Das and S. Baishya, “Analytical modelling of electrical parameters and the analogue performance of cylindrical gate-all-around FinFET,” Pramana – J. Phys, vol. 92, no. 2, October, 2018. DOI: https://doi.org/10.1007/s12043-018-1663-5
  9. Rajesh Saha, Brinda Bhowmick, amd S. Baishya, “Study on Impact of Ferroelectric Layer Thickness on RF/Analog and Linearity Parameters in Ferroelectric-FinFET,” International Journal of RF and Microwave Computer-Aided Engineering, vol. 31, no. 8, pp. e22704, August 2021. DOI: http://dx.doi.org/10.1002/mmce.22704
  10. Radhe Govinda Debnath and S. Baishya, “Impact of source-doping gradient in terms of lateral straggle on the performance of germanium epitaxial layer double-gate TFET,” Applied Physics A, vol. 126, pp. 907,October, 2020. DOI: https://doi.org/10.1007/s00339-020-04084-2
  11. Sanjoy Debnath, Wasim Arif, and S. Baishya, “Buyer Inspired Meta-Heuristic Optimization Algorithm,” Open Computer Science, vol. 10, pp. 194-219, July, 2020. DOI: DOI: https://doi.org/10.1515/comp-2020-0101
  12. Moumita Pal, C. Lalengkima, Reshmi Maity, S. Baishya, and N. P. Maity, “Effects of fringing capacitances and electrode’s finiteness in improved SiC membrane based micromachined ultrasonic transducers,” Microdystem Technologies, January, 2021. DOI: https://doi.org/10.1007/s00542-020-05135-7
  13. Suparna Panchanan, Reshmi Maity, S. Baishya, and N. P. Maity, “A surface potential model for tri-gate metal oxide semiconductor field effect transistor: Analysis below 10 nm channel length,” Engineering Science and Technology, an International Journal, February, 2021. DOI: https://doi.org/10.1016/j.jestch.2020.12.020
  14. Rajesh Saha, Brinda Bhowmick, amd S. Baishya, “Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET,” Ferroelectrics, vol. 570, pp. 67-76, January, 2021. DOI: https://doi.org/10.1080/00150193.2020.1839256
  15. Rajesh Saha, Deepak Kumar Panda, Rupam Goswami, Brinda Bhowmick, and S. Baishya. “Analysis on Effect of Lateral Straggle on Analog, High Frequency and DC Parameters in Ge-source DMDG TFET,” International Journal of RF and Microwave Computer-Aided Engineering, February, 2021. DOI: http://dx.doi.org/10.1002/mmce.22579
  16. Pragati Singh, Rudra Sankar Dhar, S. Baishya, and Amitabh Chatterjee, “Bipolar effects in snapback mechanism in advanced n-FET transistors under high current stress conditions,” Journal of Physics Communications, vol. 4, no. 6, pp. 065009, June, 2020. DOI: https://doi.org/10.1088/2399-6528/ab9954
  17. Debika Das, S. Baishya, and Ujjal Chakraborty, “Impact of temperature on RF characteristics and electrical noise analysis of an L‐shaped gate tunnel FET with hetero‐stacked source configuration,” International Journal of RF and Microwave Computer-Aided Engineering, June, 2020. Doi: https://doi.org/10.1002/mmce.22310
  18. Kuheli Roy Barman and S. Baishya, “Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET,” Silicon, July, 2020. Doi: https://doi.org/10.1007/s12633-020-00561-8
  19. Radhe Gobinda Debnath, Karabi Barua, and S. Baishya, “DC and analog/RF performance analysis of gate extended U-shaped channel tunnel field effect transistor,” Microsystem Technologies, vol. 26, pp. 2793–2799, 2020. DOI: https://doi.org/10.1007/s00542-020-04846-1
  20. Sanjoy Debnath, S. Baishya, Debarati Sen, and Wasim Arif, “A hybrid memory‑based dragonfly algorithm with differential evolution for engineering application,” Engineering with Computers, February, 2020. DOI: https://doi.org/10.1007/s00366-020-00958-4
  21. Karabi Baruah, Rajashree Das, and S. Baishya, “ Impact of Trap Charge and Temperature on DC and Analog/RF Performances of Hetero Structure Overlapped PNPN Tunnel FET,” Applied Physics A. vol. 126, pp. 856, October, 2020. DOI: 10.1007/s00339-020-04054-8
  22. Achinta Baidya, T. R. Lenka, and S. Baishya, “Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-k Dielectrics and Gate Metals,” Silicon, August, 2020. DOI: https://doi.org/10.1007/s12633-020-00669-x
  23. Suparna Panchanan, Reshmi Maity, S. Baishya, and N. P. Maity, “Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET,” Silicon, october, 2020. DOI: https://doi.org/10.1007/s12633-020-00607-x
  24. Himeli Chakraborti, Reshmi Maity, N. P. Maity, and S. Baishya, “An Accurate Model for Threshold Voltage Analysis of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor,” Silicon, July, 2020. DOI 10.1007/s12633-020-00553-8
  25. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Impact of Work Function on Analog/RF and Linearity Parameters in Step-FinFET,” Indian Journal of Physics, October, 2020. DOI: https://doi.org/10.1007/s12648-020-01895-0
  26. Rajesh Saha, Rupam Goswami, Brinda Bhowmick, and S. Baishya, “Dependence of RF/Analog and Linearity Figure of Merits on Temperature in Ferroelectric FinFET: A Simulation Study,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 67, no. 11, pp. 2433-2439, November, 2020, DOI 10.1109/TUFFC.2020.2999518
  27. Sanjoy Debnath, S. Baishya, Debarati Sen, and Wasim Arif, “A hybrid memory-based dragonfly algorithm with differential evolution for engineering application,” Engineering with Computers, February, 2020. DOI: https://doi.org/10.1007/s00366-020-00958-4
  28. N. P. Maity, Reshmi Maity, Subir Dutta, Subhasish Deb, K. Girija Srayani, K. Srinivasa Rao, and S. Baishya, “Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor, Transactions on Electrical and Electronic Materials, vol. 21, pp. 339–347, 2020, DOI: https://doi.org/10.1007/s42341-020-00181-4
  29. Rajashree Das, Brinda Bhowmick, and S. Baishya, “Robustness to Ambipolarity and Improvement to HF FOMs of Dual-Stacked-Gate Dielectrics Underlap Heterojunction TFETs,” Indian Journal of Physics, August, 2020. DOI: https://doi.org/10.1007/s12648-020-01821-4
  30. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Impact of Lateral Straggle on Linearity Performance in Gate-Modulated (GM) TFET,” Applied Physics A, vol. 126, no.3, pp. 201, February, 2020. DOI: https://doi.org/10.1007/s00339-020-3373-3
  31. Kuheli Roy Barman and S. Baishya, “An Insight to the Performance of Vertical Super-Thin Body (VSTB) FET in Presence of Interface Traps and Corresponding Noise and RF Characteristics,” Applied Physics A, vol. 125, pp. 865, 2019. DOI: https://doi.org/10.1007/s00339-019-3165-9
  32. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET,” Microelectronics Engineering, vol. 214, pp. 1-4, June, 2019. DOI: https://doi.org/10.1016/j.mee.2019.04.024
  33. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Impact of Mole Fractions due to Work Function Variability (WFV) of Metal Gate on Electrical Parameters in strained SOI-FinFET,” Silicon, vol. 12, no. 3, pp. 577-583, March, 2020. DOI: https://doi.org/10.1007/s12633-019-00163-z
  34. Koushik Guha, Hrishikesh Dutta, Jasti Sateesh, S. Baishya, and K. Srinivasa Rao, “Design and analysis of perforated MEMS resonator,” Microsystem technologies, vol. 27, pp. 613-617, February, 2021. DOI: https://doi.org/10.1007/s00542-018-4207-5
  35. Achinta Baidya, T. R. lenka, and S. Baishya, “3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications,” IETE Journal of Research, August, 2019. DOI: https://doi.org/10.1080/03772063.2019.1649203
  36. Reshmi Meity, Niladri Pratap Meity, and S. Baishya, “An Efficient Model of Nanoelectromechanical Systems Based Ultrasonic Sensor With Fringing Field Effects,” IEEE Sensors Journal, vol. 20, no. 4, pp. 1746-1753, February, 2020. DOI: 10.1109/JSEN.2019.2948795
  37. Kuheli Roy Barman and S. Baishya, “Performance Analysis of Vertical Super-Thin Body (VSTB) FET and its Characteristics in Presence of Noise,” Applied Physics A, vol. 125, no. 6, pp. 401, June, 2019. DOI: 10.1007/s00339-019-2682-x
  38. Reshmi Maity, N. P. Maity, Srinivasa Rao, Girija Sravani, Koushik Guha, and S. Baishya, “Fringing Capacitive Effect of Silicon Carbide Based Nano-Electro-Mechanical-System Micromachined Ultrasonic Transducers: Analytical Modeling and FEM Simulation,” Transactions on Electrical and Electronic Materials, vol. 20, no. 5, pp. 473–480, October 2019. DOI: https://doi.org/10.1007/s42341-019-00127-5
  39. N. P. Maity, Reshmi Maity, and S. Baishya, “An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET,” Journal of Computational Electronics, vol. 18, no. 1, pp. 65-75, 2019. DOI: https://doi.org/10.1007/s10825-018-1279-5
  40. Rajashree Das and S. Baishya, “Electrical parameter analysis of gate-extension on source of germanium tri-gate FinFET,” International Journal of Nanoparticles, vol. 11, no. 2, pp. 130-139, March 2019. DOI: https://doi.org/10.1504/IJNP.2019.099183
  41. N. P. Maity, Reshmi Maity, S. Maity and S. Baishya, “A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-threshold Regime: Application to High-k Material HfO2,” Journal of Nanoelectronics and Optoelectronics, vol. 14, no. 6, pp. 868-876, June 2019. DOI: https://doi.org/10.1166/jno.2019.2547
  42. N. P. Maity, Reshmi Maity, S. Maity, and S. Baishya, “Comparative Analysis of the Quantum FinFET and Trigate FinFET Based on Modeling and Simulation,” Journal of Computational Electronics, vol. 18. No. 2, pp. 492-499, June, 2019. DOI: https://doi.org/10.1007/s10825-018-01294-z
  43. Sweta Chander, S. Baishya, S. K. Sinha, S. Kumar, P. K. Singh, K. Baral, M. R. Tripathy, A. K. Singh, and S. Jit, “Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs,” Superlattices and Microstructures, vol. 131, pp. 30-39, July, 2019. DOI: https://doi.org/10.1016/j.spmi.2019.05.037
  44. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Quantum Modeling of Threshold Voltage in Ge Dual Material Gate (DMG) FinFET,” Solid-State Electronics, vol. 159, pp. 129-134, September, 2019. DOI: https://doi.org/10.1016/j.sse.2019.03.047
  45. Rajashree Das and S. Baishya, “Analytical modeling of threshold voltage and subthreshold swing in Si/Ge heterojunction FinFET,” Applied Physics A, vol. 125, no. 10, pp. 682, October, 2019. DOI: https://doi.org/10.1007/s00339-019-2969-y
  46. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Deep insights into electrical parameters due to metal gate WFV for different gate oxide thickness in Si step FinFET,” Micro & Nano Letters, vol. 14, no. 4, pp. 384 – 388, April 2019. DOI: 10.1049/mnl.2018.5220
  47. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Analytical Threshold Voltage and Subthreshold Swing model for TMG FinFET,” International Journal of Electronics, vol. 106, pp. 553-566, no. 4, 2019. DOI: https://doi.org/10.1080/00207217.2018.1545258
  48. Rajashree Das and S. Baishya, “Dual-Material Gate Dual-stacked Gate Dielectrics Gate-Source Overlap Tri-Gate Germanium FinFET: Analysis and Application,” Indian Journal of Physics, vol. 93, pp. 197-205, no. 2, February, 2019. DOI: https://doi.org/10.1007/s12648-018-1289-y
  49. Rajashree Das and S. Baishya, “Analytical modeling of electrical parameters and the analogue performance of Cylindrical gate-all-around FinFET,” Pramana-Journal of Physics, vol. 92, pp. 2 (10), 2019. DOI: https://doi.org/10.1007/s12043-018-1663-5
  50. Rajesh Saha, Brinda Bhowmick, K. Vanlalawmpuiab, and S. Baishya, “Deep Insight into DC, RF/Analog, and Digital Inverter Performance Due to Variation in Straggle Parameter for Gate Modulated TFET,” Materials Science in Semiconductor Processing, vol. 91, pp. 102-107, March 2019. DOI: https://doi.org/10.1016/j.mssp.2018.11.011
  51. N. P. Maity, Reshmi Maity, and S. Baishya, “The influence of image force effect on the accuracy of modeling of tunneling current for ultra thin high-k dielectric material Ta2O5 based MOS devices,” Materials Today: Proceeedings, vol. 5, no. 7, pp. 15104-15109, 2018
  52. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Temperature Effect on RF/Analog and Linearity Parameters in DMG FinFET,” Applied Physics A, vol. 124, pp. 642 (1-10), 2018. DOI: https://doi.org/10.1007/s00339-018-2068-5
  53. Reshmi Maity, N. P. Maity, K. Srinivasa Rao, K. Guha, and S. Baishya, “A New Compact Analytical Model of Nanoelectromechanical Systems-based Capacitive Micromachined Ultrasonic Transducers for Pulse Echo Imaging,” Journal of Computational Electronics, vol. 17, pp. 1334–1342, 2018. DOI: https://doi.org/10.1007/s10825-018-1178-9
  54. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET,” Micro & Nano Letters, vol. 13. No. 7, pp. 1007-1010, July 2018. DOI: 10.1049/mnl.2018.0189
  55. Reshmi Maity, N. P. Maity, Koushik Guha, and S. Baishya, “Analysis of fringing capacitance effect on the performance of micro-electromechanical-system-based micromachined ultrasonic air transducer,” Micro & Nano Letters, vol. 13, no. 6, pp. 872-877, June 2018. DOI: 10.1049/mnl.2017.0688
  56. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Comparative Analysis Among Single Material Gate, Double Material Gate, and Triple Material Gate FinFETs: RF/Analog and Digital Inverter Performance,” Journal of Nanoelectronics and Optoelectronics, vol. 13, no. 6, pp. 803-811, June 2018. DOI: https://doi.org/10.1166/jno.2018.2336
  57. Rajashree Das and S. Baishya, “Analytical Model of Surface Potential and Threshold Voltage in Gate-Drain Overlap FinFET,” Microelectronics Journal, vol. 75, pp. 153-159, May 2018. DOI: https://doi.org/10.1016/j.mejo.2018.04.005
  58. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Effect of Ge mole fraction on electrical parameters of Si1-xGex source step-FinFET and its application as an inverter,” Silicon, available online. DOI: https://doi.org/10.1007/s12633-018-9846-8
  59. Shanidul Hoque, Wasim Arif, Debarati Sen, and S. Baishya, “Analysis of Spectrum Handoff under General Residual Time Distributions of Spectrum Holes in Cognitive Radio Networks,” Journal of Information Science and Engineering, vol. 34, no. 4, pp. 851-867, 2018. DOI: 10.6688/JISE.201807_34(4).0004
  60. Rajashree Das and S. Baishya, “Investigation on Effect of Temperature on Dual Gate Material Gate/Drain Underlap Germanium FinFET,” Journal of Nanoelectronics and Optoelectronics, vol. 13, no. 7, July 2018. DOI: https://doi.org/10.1166/jno.2018.2339
  61. Rajashree Das and S. Baishya, “Analysis of GaN Nanoscale FinFET for Low Power Circuit Applications,” Micro & Nano Letters, vol. 13, no. 4, pp. 568-571, 2018. DOI: 10.1049/mnl.2017.0795
  62. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Quantum Analytical Modeling of Inversion Charge and Threshold Voltage in Modified Bi-Level FinFET (BL-FinFET),” ECS Journal of Solid State Science and Technology, vol. 7, no. 2, pp. Q8-Q15, 2018. DOI: 10.1149/2.0231802jss
  63. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “A 3D Statistical Simulation Study of Titanium Metal Gate WFV on Electrical Parameters in n-channel Ge step-FinFET,” Applied Physics A – Materials Science & Processing, vol. 124, 96(1-11), 2018. DOI: https://doi.org/10.1007/s00339-017-1545-6
  64. Rajashree Das and S. Baishya, “Controlling the fixed trap charge effect in FinFET using heterodielectric BOX,” Electronics Letters, vol. 54, no. 4, pp. 239-240, February, 2018. DOI: 10.1049/el.2017.3803
  65. S. Baishya, Debarun Borthakur, Richik Kashyap, and Amitabh Chatterjee, “A High Precision Lumped Parameter Model for Piezoelectric Energy Harvesters,” IEEE Sensors Journal, vol. 17, no. 24, pp. 8350-8355, December 2017. DOI: 10.1109/JSEN.2017.2764165
  66. N. P. Maity, Reshmi Maity, and S. Baishya , “A Tunneling Current Model with a Realistic Barrier for Ultra Thin High-k Dielectric ZrO2 Material Based MOS Devices,” Silicon, vol. 10, no. 4, pp. 1645-1652, July 2018. DOI: https://doi.org/10.1007/s12633-017-9648-4 (SCI-E)
  67. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “3D Analytical Modeling of Surface Potential, Threshold Voltage, and Subthreshold Swing in Dual Material Gate (DMG) SOI FinFET,” Journal of Computational Electronics, vol. 17, pp. 153-162, 2018. DOI: https://doi.org/10.1007/s10825-017-1072-x
  68. K. Guha, N. M. Laskar, H. J. Gogoi, A. K. Borah, K. L. Baishnab, and S. Baishya, “Novel Analytical Model for Optimizing the Pull-in Voltage in a Flexured MEMS Switch Incorporating Beam Perforation Effect,” Solid-State Electronics, vol. 137, pp. 85-94, 2017, doi: https://doi.org/10.1016/j.sse.2017.08.007
  69. Achinta Baidya, S. Baishya, and T. R. Lenka, “Impact of Thin High-K Dielectrics and Gate Metals on RF Characteristics of 3D Double Gate Junctionless Transistor,” Materials Science in Semiconductor Processing, vol. 71, pp. 413-420, Nov. 2017, doi: https://doi.org/10.1016/j.mssp.2017.08.031
  70. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “GaAs SOI FinFET: Impact of Gate Dielectric on Electrical Parameters and Application as Digital Inverter,” International Journal of Nanoparticles, to be published
  71. Reshmi Maity, N. P. Maity, and S. Baishya, “Silicon Nitride Based Electro-Mechanical Model of Capacitive Micromachined Ultrasonic Transducers,” Far East Journal of Electronics and Communications, vol. 17, no. 4, pp. 749-760, 2017, doi: http://dx.doi.org/10.1a7654/EC017040749
  72. N. P. Maity, Reshmi Maity, and S. Baishya, “Voltage and Oxide Thickness Dependent Tunneling Current Density and Tunnel Resistivity Model: Application to High-k Material HfO2 Based MOS Devices,” Superlattices and Microstructures, vol. 111, pp. 628-641, 2017, doi: https://doi.org/10.1016/j.spmi.2017.07.022
  73. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Si and Ge step-FinFETs: Work function variability, optimization and electrical parameters,” Superlattices and Microstructures, vol. 107, pp. 5-16, 2047, doi: https://doi.org/10.1016/j.spmi.2017.04.001
  74. Saurav Roy, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rimma Pirogova, and S. Baishya, “Two Dimensional Analytical Modelling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body Field Effect Transistor,” IEEE Transactions on Electron Devices, vol. 84, no. 5, pp. 2106-2112, May 2017, doi: 10.1109/TED.2017.2687465.
  75. N. P. Maity, Reshmi Maity, and S. Baishya, “Ultra Thin Body Partial Silicon-on-Insulator MOSFET with Suppressed Floating Body Effect: A Simulation Study,” Journal of Nanoelectronics and Optoelectronics, vol. 12, no. 5, pp. 472-479, May 2017, doi: 10.1166/jno.2017.2039
  76. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Statistical Dependence of Gate Metal Work Function on Various Electrical Parameters for an n-channel Si step-FinFET,” IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 969-976, March 2017. doi: 10.1109/TED.2017.2657233
  77. N. P. Maity, Reshmi Maity, and S. Baishya, “Influence of Image Force Effect on Tunneling Current Density for High-k Material ZrO2 Ultra Thin Films Based MOS Devices,” Journal of Nanoelectronics and Optoelectronics, vol. 12, pp. 67-71, no. 1, January 2017.
  78. N. P. Maity, R. R. Thakur, Reshmi Maity, R. K. Thapa, and S. Baishya, “Analysis of Interface Charge Densities for High-k Dielectric Materials based Metal Oxide Semiconductor Devices,” International Journal of Nanoscience, vol. 15, nos. 5 and 6, pp. 1660011-(1-6), 2016, doi: 10.1142/S0219581X16600115
  79. Rajashree Das and S. Baishya, “Analysis of Electrical Parameters of Ge/Si Heterojunction GeOI FinFETs”, Procedia Computer Science, vol. 93, pp. 132-138, 2016, doi: 10.1016/j.procs.2016.07.192
  80. Saurabh Agarwal, Richik Kashyap, Koushik Guha, and S. Baishya, “Modeling and analysis of capacitance in consideration of the deformation in RF MEMS shunt switch, Superlattices and Microstructures, available: http://dx.doi.org/10.1016/j.spmi.2016.10.022
  81. Reshmi Maity, N. P. Maity, R. K. Thapa, and S. Baishya, “An Improved Analytical and Finite Element Method Model of Nanoelectromechanical System Based Micromachined Ultrasonic Transducers,” Microsystem Technologies, vol. 23, pp. 2163-2173, June 2017, DOI:10.1007/s00542-016-3073-2
  82. Reshmi Maity, N. P. Maity, and S. Baishya, “Circular Membrane Approximation Model with the Effect of the Finiteness of the Electrode’s Diameter of MEMS Capacitive Micromachined Ultrasonic Transducers,” Microsystem Technologies, vol. 23, no. 8, pp. 3513–3524, Aug. 2017. DOI: 10.1007/s00542-016-3184-9
  83. Rupam Goswami, Brinda Bhowmick, and S. Baishya, “Physics-based surface potential, electric field and drain current model of a δp+ gate–drain underlap nanoscale n-TFET,” Int. Journal of Electroncis, vol. 103, no. 9, pp. 1565-1579, 2016. http://dx.doi.org/10.1080/00207217.2016.1138514
  84. N. P. Maity, R. R. Thakur, Reshmi Maity, R. K. Thapa, and S. Baishya, “Analysis of Interface Charge Densities for Al2O3 Dielectric Material based Ultra Thin MOS Devices,” Procedia Computer Science, vol. 57, pp. 757 – 760, 2015, doi: 10.4028/www.scientific.net/AMM.860.25
  85. N. P. Maity, Reshmi Maity, R. K. Thapa, and S. Baishya, “Modeling and Simulation of Tunneling Current Density for Ultra Thin MOS Devices,” Applied Mechanics and Materials, vol. 860, pp. 30-34, 2017, doi:10.4028/www.scientific.net/AMM.860.30
  86. N. P. Maity, R. R. Thakur, reshmi Maity, R. K. Thapa, and S. Baishya, “Analysis of Interface Trap Densities for Al2O3 Dielectric Material Based Ultra Thin MOS Devices,” Applied Mechanics and Materials, vol. 860, pp. 25-29, 2017, doi: 10.4028/www.scientific.net/AMM.860.25
  87. Reshmi Maity, N. P. Maity, R. K. Thapa, and S. Baishya, “Characterization of Nanoscale Ultrasonic Transducer Elements as Effective Acoustical Devices,” Applied Mechanics and Materials, vol. 860, pp. 35-40, 2017, doi: 10.4028/www.scientific.net/AMM.860.3
  88. Reshmi Maity, N. P. Maity, R. K. Thapa and S. Baishya, “Investigation of Silicon Nitride as an Excellent Membrane Material for MEMS Ultrasonic Transducers,” Applied Mechanics and Materials, vol. 860, pp. 41-45, 2017, doi: 10.4028/www.scientific.net/AMM.860.41
  89. R. Maity, Ajay Singh, A. Islam, N. P. Maity, R. K. Thapa, and S. Baishya, “Lumped Electromechanical Modeling of Capacitive Micromachined Ultrasonic Transducers,” Materials Today: Proceedings, vol. 3, no. 6, pp. 2289-2294, 2016.
  90. A. Baidya, T. R. Lenka, and S. Baishya, and, “Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications,” Superlattices and Microstructures, vol. 100, pp. 14-23, Dec. 2016, doi: http://dx.doi.org/10.1016/j.spmi.2016.08.028
  91. N. P. Maity, Reshmi Maity, R. K. Thapa, and S. Baishya, “A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices,” Superlattices and Microstructures. vol. 94, pp. 24-32, 2016, http://dx.doi.org/10.1016/j.spmi.2016.04.032
  92. Rupam Goswami, Brinda Bhowmick, and S. Baishya, “Effect of Scaling on Noise in Circular Gate TFET and its Application as a Digital Inverter,” Microelectronics Journal, vol. 53, pp. 16-24, 2016, doi: http://dx.doi.org/10.1016/j.mejo.2016.04.009
  93. N. P. Maity, Reshmi Maity, and S. Baishya, “Tunneling Current Density Model with Ideal Barrier for Ultra Thin Films Al2O3 High-k Material Based MOS Devices,” Materials Focus, vol. 5, no. 3, pp. 275-280, June 2016, doi: https://doi.org/10.1166/mat.2016.1326
  94. Richik Kashyap, T. R. Lenka, and S. Baishya, “Distributed Parameter Modeling of Cantilevered d33 Mode Piezoelectric Energy Harvesters,” IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1281-1287, March 2016, doi: 10.1109/TED.2015.2514160
  95. Rajashree Das, Rupam Goswami, and S. Baishya, “Tri-gate heterojunction SOI Ge-FinFETs,” Superlattices and Microstructures, vol. 91, pp. 51-61, March 2016, doi: http://dx.doi.org/10.1016/j.spmi.2015.12.039
  96. Sweta Chander and S. Baishya, “Two-dimensional model of a heterojunction silicon-on-insulator tunnel field effect transistor,” Superlattices and microstructures, vol. 90, pp. 176-183, February 2016, doi:http://dx.doi.org/10.1016/j.spmi.2015.12.013
  97. Richik Kashyap, T. R. lenka, and S. Baishya, “A Model for Doubly Clamped Piezoelectric Energy Harvesters with Segmented Electrodes,” IEEE Electron Device Letters, vol. 36, no. 12, pp. 1369-1372, December 2015. doi: 10.1109/LED.2015.2496186
  98. N. P. Maity, Reshmi Maity, R. K. Thapa, and S. Baishya, “Image Force Effect on Tunneling Current for Ultra Thin High-K Dielectric Material Al2O3 Based Metal Oxide Semiconductor Devices,” Journal of Nanoelectronics and Optoelectronics, Vol. 10, no. 5, pp. 645-648, October 2015.
  99. S. K. Gupta and S. Baishya, “Analog and RF Performance Analysis of a Junctionless Electrically Induced Source/Drain Extension Cylindrical Surround Gate (JLEJ-CSG) MOSFET,” Journal of The Institution of Engineers (India): Series B, vol. 96, no. 3, pp. 211-216, July-September 2015, doi: 10.1007/s40031-014-0131-y
  100. Rupam Goswami, Brinda Bhowmick, and S. Baishya, “Electrical noise in Circular Gate Tunnel FET in presence of interface traps,” Superlattices and microstructures, vol. 86, pp. 342-354, October 2015, doi:http://dx.doi.org/10.1016/j.spmi.2015.07.064
  101. Koushik Guha, Mithlesh Kumar, Saurabh Agarwal, and S. Baishya, “A modified capacitance model of RF MEMS shunt switch incorporating fringing field effects of perforated beam,” Solid State Electronics, vol. 114, pp. 35-42, December 2015, doi: http://dx.doi.org/10.1016/j.sse.2015.07.008
  102. Sweta Chander, Brinda Bhowmick, and S. Baishya, “Heterojunction fully depleted SOI-TFET with oxide/source overlap,” Superlattices and microstructures, vol. 86, pp. 43-50, October 2015, doi: http://dx.doi.org/10.1016/j.spmi.2015.07.030
  103. Wasim Arif, Shanidul Hoque, Debarati Sen, and S. Baishya, “A Comprehensive Analysis of Spectrum Handoff under Different Distribution Models for Cognitive Radio Networks,” Wireless Personal Communications, vol. 85, no. 4, pp. 2519–2548, December 2015, doi: http://link.springer.com/article/10.1007/s11277-015-2918-9
  104. Sweta Chander and S. Baishya, “A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap,” IEEE Electron Device Letters, vol. 36, no. 7, pp. 714-716, July 2015, doi:10.1109/LED.2015.2432061
  105. Koushik Guha, Mithlesh Kumar, Ajay Parmar, and S. Baishya, “Performance Analysis of RF MEMS Capacitive Switch with Non Uniform Meandering Technique,” Microsystem Technologies, vol. 22, no. 11, pp. 2633–2640, doi:10.1007/s00542-015-2545-0
  106. N. P. Maity, R. R. Thakur, R. Maity, R. K. Thapa, and S. Baishya, “Analysis of Interface Charge Using Capacitance-Voltage Method for Ultra Thin HfO2 Gate Dielectric Based MOS Devices”, Procedia Computer Science, vol. 57, pp. 757 – 760, 2015, doi: 10.1016/j.procs.2015.07.470
  107. N. P. Maity, R. R. Thakur, R. Maity, R. K. Thapa, and S. Baishya, “ Interface Charge Density Measurement for Ultra Thin ZrO2 Material Based MOS Devices Using Conductance Method”, Procedia Computer Science, vol. 57, pp. 761-765, 2015, doi:10.1016/j.procs.2015.07.472
  108. Reshmi Maity, R. K. Thapa, and S. Baishya, “Analytical Characterization and Simulation of a 2-D Capacitive Micromachined Ultrasonic Transducer Array Element,” Journal of Computational and Theoretical Nanoscience, vol. 12, no. 10, pp. 3692-3696, october 2015, doi:10.1166/jctn.2015.4261
  109. Reshmi Maity, N. P. Maity, R. K. Thapa and S. Baishya, “Analysis of Frequency Response Behaviour of Capacitive Micromachined Ultrasonic Transducers”, Journal of Computational and Theoretical Nanoscience, vol. 12, no. 10, pp. 3492-3494, October 2015, doi:10.1166/jctn.2015.4227.
  110. N. P. Maity, Reshmi Maity, R. K. Thapa, and S. Baishya, “Effect of Image Force on Tunneling Current for Ultra Thin Oxide Layer Based Metal Oxide Semiconductor Devices”, Nanoscience and Nanotechnology Letters, vol. 7, no. 4, pp. 331-333, April 2015, doi:10.1166/nnl.2015.1970.
  111. A. Baidya, V. Krishnan, S. Baishya, and T.R. Lenka, “Effect of thin gate dielectrics and gate materials on simulated device characteristics of 3D double gate JNT,” Superlattices and Microstructures, vol. 77, pp. 209-218, January 2015, http://dx.doi.org/10.1016/j.spmi.2014.11.007
  112. N. P. Maity, Atul Kumar, Reshmi Maity, and S. Baishya, “Analysis of Flatband Voltage for MOS Devices Using High-K Dielectric Materials,” Procedia Materials Science, vol. 5, pp. 1198-1204, 2014, doi: 10.1016/j.mspro.2014.07.421
  113. N. P. Maity, Reshmi Maity, R. K. Thapa, and S. Baishya, “Study of Interface Charge Densities for ZrO2 and HfO2 Based Metal-Oxide-Semiconductor Devices,” Advances in Materials Science and Engineering, vol. 2014, Article ID 497274, 6 pages, 2014, doi: http://dx.doi.org/10.1155/2014/497274
  114. S. K. Gupta and S. Baishya, “On the analog and radio frequency performance of Junctionless Single Metal Gate cylindrical surround gate metal-oxide-semiconductor field-effect transistors,” Simulation-Transactions of the Society for Modeling and Simulation International, vol. 90, no. 10, pp. 1119-1128, October 2014, doi:10.1177/0037549714544336
  115. N. P. Maity, R. K. Thapa, and S. Baishya, “Comparison of different high-k dielectric materials in MOS device from CV Characteristics,” Advanced Materials Research, vol. 816-817, pp. 60-64, 2013, doi:10.4028/www.scientific.net/AMR.816-817.60. A
  116. Reshmi Maity, R. K. Thapa, and S. Baishya, “Membrane Displacement Behavior of Capacitive Micromachined Ultrasonic Transducers under Static Bias,” Advanced Materials Research , vol. 816-817, pp. 892-896, 2013, doi:10.4028/www.scientific.net/AMR.816-817.892
  117. B. Bhowmick, S. Baishya, and J. Sen “Optimization and Length Scaling of Raised Drain Buried Oxide SOI Tunnel FET,” Electronics Letters, vol. 49, no. 16, pp. 1031 – 1033, August 2013, doi: 10.1049/el.2013.1256
  118. S. K. Gupta and S. Baishya, “Modeling of Cylindrical Surrounding Gate MOSFETs Including the Fringing Field Effects”, Journal of Semiconductors, vol. 34, no. 7, pp. 074001 – 074006, 2013, doi: 10.1088/1674-4926/34/7/074001
  119. S. K. Gupta and S. Baishya, “Analog and RF Performance Evaluation of Dual Metal Double Gate High-k Stack (DMDG-HKS) MOSFETs”, Journal of Nano- and Electronic Physics, vol. 5, no. 3, pp. 03008 (1-8), 2013
  120. S. Baishya, “A Surface Potential and Quasi-Fermi Potential Based Drain Current Model for Pocket Implanted MOS Transistors in Subthreshold Regime,” Microelectronics Reliability, pp. 681 – 688, vol. 49, Jul. 2009.
  121. S. Baishya, A. Mallik, and C. K. Sarkar, “A Threshold Voltage Model for Short-Channel MOSFETs Taking into Account the Varying Depth of Channel Depletion Layers Around the Source and Drain,” Microelectronics Reliability, pp. 17 – 22, vol. 48, January 2008.
  122. S. Baishya, A. Mallik, and C. K. Sarkar, “A Pseudo-two-dimensional Subthreshold Surface Potential Model for Dual-material Gate MOSFETs,” IEEE Transactions on Electron Devices, pp. 2520 – 2525, vol. 54, September 2007.
  123. S. Baishya, A. Mallik, and C. K. Sarkar, “A Surface Potential Based Subthreshold Drain Current Model for Short-channel MOS Transistors,” Semiconductor Science & Technology, pp. 1066 – 1069, vol. 22, 2007.
  124. S. Baishya, A. Mallik, and C. K. Sarkar, “Subthreshold Surface Potential and Drain Current Models for Short-channel Pocket-implanted MOSFETs,” Microelectronic Engineering, vol. 84, pp. 653–662, April 2007.
  125. S. Baishya, A. Mallik, and C. K. Sarkar, “A Subthreshold Surface Potential Model for Short-channel MOSFET Taking into Account the Varying Depth of Channel Depletion Layer due to Source and Drain Junctions,” IEEE Transactions on Electron Devices, vol. 53, pp. 507–514, March 2006.
  126. S. Baishya, S. Chakraborty, A. Mallik, and C. K. Sarkar, “A Subthreshold Surface Potential and Drain Current Model for Lateral Asymmetric Channel (LAC) MOSFETs,” IETE Journal of Research, vol. 52, pp. 379–390, September-October 2006.

Conferences

  1. Sanjoy Debnath, Anand Jee, S. Baishya, Wasim Arif, Partha Pratim Saikia, and Shoaib Naafi, “Access Point Planning for Disaster Scenario using Dragonfly Algorithm,” In Proc. 2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), pp. 226-231, 22-23 Feb. 2018, Noida, India. DOI: 10.1109/SPIN.2018.8474051
  2. Koushik Guha, S. Baishya, and Ananta Kumar Borah, “New analytical model of switching capacitance for MEMS shunt perforated switch,” in Proc. 2017 IEEE 12th Nanotechnology Materials and Devices Conference (NMDC), pp. 107-108, October 2-4, 2017, Singapore. DOI: 10.1109/NMDC.2017.8350521
  3. Achinta Baidya, T. R. Lenka, and S. Baishya, “Inverter Performance Analysis of 3D Double Gate Junctionless Transistor,” in Proc. 2017 2nd International Conference on Communication and Electronics Systems (ICCES), pp. 798-802, 19-20 October 2017, Coimbatore, India. DOI: 10.1109/CESYS.2017.8321194
  4. Debarun Borthakur, S. Baishya, and Sweta Chander, “Optimization of Piezoelectric Energy Harvesting Structure by Segmenting the Piezoelectric Layer(s),” in Proc. 2017 IEEE Nanotechnology Material and Devices Conference, pp. 13-14, October 2-4, 2017, Singapore. DOI: 10.1109/NMDC.2017.8350485
  5. Shanidul Hoque, Ram Kumar Karsh, Srimanta Baishya, and Wasim Arif, “Spectrum Handoff Performance in Opportunistic and Negotiated Situations for Cognitive Radio Networks,” in Proc. 2017 IEEE Region 10 Conf. (TENCON). DOI: 10.1109/TENCON.2017.8228156
  6. Chandrashekhar Rai, Sanjoy Debnath, S. Baishya, and Wasim Arif, “Secondary User Capacity Maximization in CR under Nakagami-m Fading Channel with Receiver Diversity,” in Proc. 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech). DOI: 10.1109/IEMENTECH.2017.8077003
  7. Rajashree Das and S. Baishya, “Dual stacked gate dielectric source/oxide overlap Si/Ge FinFETs: Proposal and analysis,” in Proc. 2017 Devices for Integrated Circuit (DevIC), pp. 66-70, Oct. 2017. DOI: 10.1109/DEVIC.2017.8073908
  8. Rajesh Saha, Brinda Bhowmick, and S. Baishya, “Effects of temperature on electrical parameters in GaAs SOI FinFET and application as digital inverter,” in Proc. 2017 Devices for Integrated Circuit (DevIC), pp. 462-466, Oct. 2017. DOI: 10.1109/DEVIC.2017.8073992
  9. Pankaj Kumar, Saurav Roy, and S. Baishya, “Gate-overlapped-source heterojunction tunnel tri-gate FinFET,” in Proc. 2017 Devices for Integrated Circuit (DevIC), pp. 561-564, Oct. 2017. DOI: 10.1109/DEVIC.2017.8074013
  10. Achinta Baidya, T. R. Lenka, and S. Baishya, “Application of 3D Double Gate Junctionless Transistor for Ring Oscillator,” in Proc. IEEE International Conference on Recent Advance and Innovation in Engineering (ICRAIE 2016), 1016. DOI: 10.1109/ICRAIE.2016.7939580
  11. Ritwik Haldar, Koushik Guha, and S. Baishya, “Effect on Pull-in Voltage and Current in NEMFET by Scaling Channel Length,” in Proc. IEEE TENCON 2015, doi: 10.1109/TENCON.2015.7373022
  12. Sweta Chander, Rajashree Das, and S. Baishya, “Improved Miller Capacitance of New Heterostructure Silicon-on-Insulator Tunnel FET,” in Proc. IEEE TENCON 2015, doi: 10.1109/TENCON.2015.7373123
  13. A. Baidya, T. R. Lenka, and S. Baishya, “Performance Analysis and Improvement of Nanoscale Double Gate Junctionless Transistor Based Inverter Using High-K Gate Dielectrics,” in Proc. IEEE TENCON 2015, doi: 10.1109/TENCON.2015.7373040
  14. Pralay Chakraborty, K. Guha, and S. Baishya, “Performance Analysis of 3D Flexure FET with Meandering Gate for Higher Sensitivity,” in Proc. IEEE TENCON 2015, doi: 10.1109/TENCON.2015.7373072
  15. Koushik Guha, M. Kumar, R. K. Karsh, R. Rava, A. Dutta, S. Nath, and S. Baishya, “Static and Electromagnetic Analysis of RF MEMS Shunt Capacitive Switch,” in Proc. IEEE TENCON 2015, doi: 10.1109/TENCON.2015.7373072
  16. Pralay Chakrabarty, Koushik Guha, Gautam Krishna, and S. Baishya, “Comparative Analysis of 3D Flexure Gate FET with different metal and gate structure,” in Proc. 2015 Int. Conf. on Innovations in Information, embedded and Communication System (ICIIECS), doi: 10.1109/ICIIECS.2015.7193079
  17. Saurabh Agarwal, Mithlesh Kumar, Koushik Guha, and S. Baishya, “RF Analysis of MEMS Shunt Capacitive Switch with Gold and Aluminium Beam,” in Proc. 2015 Int. Conf. on Advances in Computer Engineering and Applications (ICACEA), Ghaziabad, India, pp. 267-271, doi: 10.1109/ICACEA.2015.7164713
  18. Wasim Arif, Shanidul Hoque, Debarati Sen, S. Baishya, and Aakriti Chaubey, “Sensing Time Minimization using Pipelining in Two Stage Spectrum Sensing feasibility ,” in Proc. 2015 2nd Int. Conf. on Signal Processing and Integrated Networks (SPIN), Noida, India, pp. 359-365. doi: 10.1109/SPIN.2015.7095424
  19. Sanjay Debnath, G. Sachin reddy, Shanidul Hoque, Wasim Arif, and S. Baishya, “Optimization of Spectrum Handoff Probability in Cognitive radio Networks,” in Proc. Int. Conf. on Computing, Communication, Electrical, Electronics, Devices and Signal Processing (CCEEDS) and Int. Conf. Electrical, Electronics, Engineering Trends, Communication, Optimization and Sciences (EEECOS/E3COS), Lankapalli (Challapalli), India, 2015, pp. 778-784
  20. Pralay Chakrabarty, Koushik Guha, Gautam Krishna, and S. Baishya, “Comparative Analysis of 3D Flexure Gate FET with different metal and gate structure,” in Proc. 2015 Int. Conf. on Innovations in Information, Embedded and Communication System (ICIIECS), doi: 10.1109/ICIIECS.2015.7193079
  21. Sweta Chander and S. Baishya, “A Comprehensive Analysis of SOI-TFET with Novel AlxGa1-xAs Channel Material,” in Proc. 2014 second Int. Conf. on Devices, Circuits and Systems (ICDCS), Coimbatore, India, doi: 10.1109/ICDCSyst.2014.6926155
  22. Sweta Chander and S. Baishya, “A Comprehensive Analysis of SOI-TFET with Novel AlxGa1-xAs Channel Material,” in Proc. 2014 second Int. Conf. on Devices, Circuits and Systems (ICDCS), Coimbatore, India, doi: 10.1109/ICDCSyst.2014.6926155
  23. B. Bhowmick, K. Jena, and S. Baishya, “A Self-Consistent Model for Hetero-Gate All Around Tunnel FET,” in Proc. 2014 2nd Int. Conf. on Devices, Circuits and Systems (ICDCS), Coimbatore, India, doi: 10.1109/ICDCSyst.2014.6926147
  24. B. P. Kumar, G. Amarnath, W. Arif, and S. Baishya, “An improved gate capacitance for two dimensional junctionless transistor,” in Proc. 2014 Int. Conf. on Green Computing Communication and Electrical Engineering (ICGCCEE), doi: 10.1109/ICGCCEE.2014.6922275
  25. B. Prashanth Kumar, Wasim Arif, and S. Baishya, “An inclusive study on characteristics of junctionless transistor,” in Proc. 2014 Int. Conf. on Electronics and Communication Systems (ICECS), doi: 10.1109/ECS.2014.6892746
  26. Brinda Bhowmick, S. Baishya, R. Goswami, B. Das, and C. Joishi, “An Optimized SOI g-TFET and its application in a Half Adder Circuit,” in Proc. 2014 2nd Int. Conf. on Devices, Circuits and Systems (ICDCS), doi: 10.1109/ICDCSyst.2014.6926156
  27. Sweta Chander, Om Prakash Mahto, Vivek Chander and S. Baishya, “Analysis of Novel SGOI-TFET with Record Low Subthreshold Swing (SS) and High Ion/Ioff Ratio,” in Proc. 2014 Int. Conf. on Computing for Sustainable Global Development (INDIACom), New Delhi, India, pp. 500-504, doi: 10.1109/IndiaCom.2014.6828188
  28. Shanidul Hoque, W. Arif, S. Baishya, M. Singh, and R. Singh, “Analysis of Spectrum Handoff Under Diverse Mobile Traffic Distribution Model in Cognitive Radio,” in Proc. 2014 Int. Conf. on Devices, Circuits and Communications (ICDCCom), doi: 10.1109/ICDCCom.2014.7024696
  29. Soumen Deb and S. Baishya, “Modeling and Simulation of DC Characteristics of a Novel NMOS based High Pressure Sensor,” in Proc. 2014 Int. Conf. for Convergence of Technology (I2CT), doi: 10.1109/I2CT.2014.7092211
  30. S. Baishya and Soumen Deb, “Modeling and Simulation study of AC Characteristics of an NMOS based High Pressure Sensor,” in Proc. 2014 Int. Conf. on Green Computing, Communication and Electrical Engineering (ICGCCEE), doi: 10.1109/ICGCCEE.2014.6922247
  31. Soumen Deb and S. Baishya, “TCAD Based Study of a Noble 24 nm DMIDG MOSFET for Low Power Applications, “ in Proc. 2014 Int. Conf. on Green Computing, Communication and Electrical Engineering, doi: 10.1109/ICGCCEE.2014.6921414
  32. S. Baishya and Soumen Deb, “TCAD Based Study of a Novel 24 nm Quantum Well Symmetric IDG NMOS Transistor with ultra-low Ioff,” in Proc. 2014 Int. Conf. for Convergence of Technology (I2CT), Pune, India, doi: 10.1109/I2CT.2014.7092215
  33. Sweta Chander, Om Prakash Mahto, and S. Baishya, “Analysis of novel SGOI-TFET with record low subthreshold swing (SS) and high Ion/Ioff ratio,” In Proc. 2014 Int. Conf. on Computing for Sustainable Global Development (INDIACom), New Delhi, India, pp. 500-504, doi: 10.1109/IndiaCom.2014.6828188
  34. Koushik Guha, Mithlesh Kumar, Ajay Parmar, and S. Baishya, “Non Uniform Meander Based Low Actuation Voltage High Capacitance Ratio RF MEMS Shunt Capacitive Switch,” in Proc. 2014 9th IEEE Nanotechnology Materials and Devices Conf. (NMDC), Aci Castello, Italy, pp. 120-123, doi: 10.1109/NMDC.2014.6997437
  35. Rahul Sharma and S. Baishya, “TCAD Simulation for Low Power UTBB FDSOI CMOS Device” in Proc. 2014 Int. Conf. on Green Computing, Communication and Electrical Engineering (ICGCCEE), doi: 10.1109/ICGCCEE.2014.6922240
  36. Reshmi Maity, N. P. Maity, R. K. Thapa and S. Baishya, “Impedance Response Behavior of Capacitive Micromachined Ultrasonic Transducers (CMUTs)”, in Proc. Int. Conf. on Advances in Engineering and Technology, Jameshedpur, 2014, pp. 1-3
  37. Koushik Guha, Purbashis Ganguly, and S. Baishya, “Performance analysis of low power and high frequency novel RF Power Amplifier for 4G systems,” in Proc. 2013 Int. Conf. on Electron Devices and Solid-State Circuits (EDSSC), doi: 10.1109/EDSSC.2013.6628180
  38. S. K. Gupta and S. Baishya, “Analog and RF Performance Evaluation of a Novel Junctionless Triple Metal Cylindrical Surround Gate (JLTM CSG) MOSFET,” in Proc. 2013 Annu. IEEE India Conf. (INDICON), doi: 10.1109/INDCON.2013.6725899
  39. S. K. Gupta and S. Baishya, “Effect of High-k Gate Materials on Analog and RF Performance of Double Metal Double Gate (DMDG) MOSFETs,” In Proc. 2013 Annu. IEEE India Conference (INDICON), doi: 10.1109/INDCON.2013.6725900
  40. B. Bhowmick, S. Baishya, and C. Joishy “Compact Models for double gate hetero gate Dielectric Nano scale Tunnel FET,” in Proc. of 2013 IEEE Int. Conf. on Signal processing, computing and control (ISPCC), doi: 10.1109/ISPCC.2013.6663448
  41. Sweta Chander and S. Baishya, “Impact of Channel Length & Oxide Thickness Variation in an Asymmetric SGOI-TFET,” in Proc. IEEE Asia Pacific Conf. on Postgraduate Research in Microelectronics and Electronics, Visakhapatnam, India, pp.103-106, doi: 10.1109/PrimeAsia.2013.6731186
  42. Satya Narayan Mishra, Wasim Arif, Jishan Mehedi, and S. Baishya, “A Power Efficient 6-Bit TIQ ADC Design for Portable Applications,” In Proc. 2013 IEEE 3rd Int. Conf. on Consumer Electronics – Berlin (ICCE-Berlin), Berlin, Germany, pp. 235-239, doi: 10.1109/ICCE-Berlin.2013.6698042
  43. B. Bhowmick and S. Baishya, “Drain Current Model for Ballistic Double Gate Dielectric Tunnel FET and its Mixed Mode Application,” In Proc. Int. Conf. on ComNet, CIIT and ITC, Mumbai, India, 2013, pp. 352-356, http://searchdl.org/index.php/book_series/downloadPDF/1981
  44. B. Bhowmick, S. Baishya, and K. Jena “Digital circuit performance of SiGe pocket high-k gate dielectric SOI tunnel FET,” in Proc. Int. Conf. on Control, Communication and Power Engineering (CCPE 2013), Bangalore, India, pp. 232-236
  45. B. Bhowmick and S. Baishya, “Mixed Mode Analysis of Raised Buried Oxide Tunnel FET,” in Proc. World Congress on Engineering (WCE 2012), London, UK, 4-6 July, 2012
  46. B. Bhowmick, S. Baishya, and R. Kar “Length scaling of Hetero Gate Dielectric SOI PNPN TFET,” in Proc. 2011 Annu. IEEE India Conf. (INDICON), doi: 10.1109/INDCON.2011.6139465
  47. B. Bhowmick, S. Baishya, and J. Sen, “Capacitance Measurement of a SOI Tunnel FET,” in Proc. Int. Conf. on Advances in Electrical Engineering (ICAEE), Dhaka, Bangladesh, 2011, pp. 264 – 267
  48. P. K. Patowari, J. Saikia, P. S. Chatterjee, A. Ramachandran, Ashwin P.G., and S. Baishya, “Analysis of a Comb Type Microactuator Used in Micro Thermal Switches,” In Proc. World Congress on Engineering, London, U.K., 6-8 July, 2011
  49. B. Bhowmick and S. Baishya, “Heterogate Double Gate Dielectric Tunnel FET With Record High on/off Current Ratio,” in Proc. Int. Conf. on VLSI, Communication, and Instrumentation (ICVCI), Kottayam, India, 2011, pp. 7 – 9
  50. B. Bhowmick and S. Baishya, “Performance Analysis of Double Hetero-gate Tunnel Field Effect Transistor”, in Proc. 2nd Int. Conf. on Advances in Electrical and Electronics (AEE), Noida, India, 2011, pp. 157 – 160, doi: 02.AEE.2011.02.513
  51. S. K. Gupta, Kaushik Guha, and S. Baishya, “A Two Dimensional Surface Potential Model of Double Material Double Gate Surround Gate (DMDG-SG) MOSFETs”, in Proc. of the International Conference on Artificial Intelligence and Machine Learning (AIML), Dubai, UAE, 12-14 April, 2011, pp. 143 – 147
  52. Satyanand Namana and S. Baishya, “Threshold Voltage Modelling of Drain/Source Edge Effect on Double Gate MOS Transistor,” in Proc. of the International Conference of Artificial Intelligence and Machine Learning (AIML), Dubai, UAE, 12-14 April, 2011, pp. 155-159
  53. S. K. Gupta and S. Baishya, “3D-TCAD Simulation Study of an Electrically Induced Source/Drain Cylindrically Surrounding Gate MOSFETs for Reduced SCEs and HCEs”, in Proc. 2011 3rd Int. Conf. on Electronics Computer Technology (ICECT),” Kanyakumari, India, 8-10 April, vol. 2, pp. 429 – 432. doi: 10.1109/ICECTECH.2011.5941732
  54. S. K. Gupta, Achinta Baidya, and S. Baishya, “Simulation and Optimization of Lightly-Doped Ultra-Thin Triple Metal Double Gate (TM-DG) MOSFET with High-K Dielectric for Diminished Short Channel Effects”, in Proc. 2011 Int. Conf. on Computer and Communication Technology (ICCCT), MNNIT Allahabad, India, 15-17 September, pp. 221–224, doi: 10.1109/ICCCT.2011.6075167
  55. B. Bhowmick, S. Baishya, and R. Kar, “Length Scaling of Hetero-gate Dielectric SOI PNPN TFET,” in Proc. 2011 Annu. IEEE India Conf. (INDICON), Hyderabad, India, 16-18 December, doi: 10.1109/INDCON.2011.6139465
  56. R. H. Laskar, S. Baishya, Saurav K. Kar, Rajib Sharma, N. Medhi, and R. D. Purkayastha, “Color Image Denoising in Wavelet Domain Using Adaptive Thresholding Incorporating the Human Visual System Model,” in Proc. 6th Int. Conf. on Electrical and Computer Engineering (ICECE), Dhaka, Bangladesh, 18-20 December, pp. 498 – 501, doi: 10.1109/ICELCE.2010.5700738
  57. Satyanand Namana, S. Baishya, and Kalyan Koley, “A Subthreshold Surface Potential Modeling of Drain/Source Edge Effect on Double Gate MOS Transistor,” in Proc. 2010 Int. Conf. on Electronics and Information Engineering (ICEIE), Kyoto, Japan, 1-3 August, pp. V1-87–V1-91, doi: 10.1109/ICEIE.2010.5559844
  58. V. Ramanjaneyulu, S. Baishya, and R. H. Laskar, “Optimization Consideration of Undoped Raised Source/drain FinFET with Effective SCE Control,” in Proc. 2010 2nd Int. Conf. on Electronics and Mechanical Engineering (ICMEE), Kyoto, Japan, 1-3 August, pp. V1-150 – V1-153, doi: 10.1109/ICMEE.2010.5558575
  59. A. K. Bharali, P. K. Patowari, and S. Baishya, “Design and Analysis of Multilayer Electrothermal Actuator for MEMS,” in Proc. 2010 2nd Int. Conf. on Electronics and Mechanical Engineering (ICMEE), Kyoto, Japan, 1-3 August, pp. V1-127 – V1-131, doi: 10.1109/ICMEE.2010.5558582
  60. Kalyan Koley and S. Baishya, “A Subthreshold Surface Potential Modeling of Drain/Source Edge Effect in MOS Transistors,” in Proc. 2010 3rd IEEE Int. Conf. on Computer Science and Information Technology (ICCSIT), 9-11 July, pp. 157 – 161, doi: 10.1109/ICCSIT.2010.5564725
  61. Brinda Bhowmick and S. Baishya, “Hetero double gate-dielectric Tunnel FET with record high Ion/Ioff Ratio,” In Proc. Int. Conf. on VLSI, Communication and Instrumentation (ICVCI 2011), Kottayam, India, pp. 11-13
  62. A. Sarkar, S. De, M. Nagarajan, C. K. Sarkar, and S. Baishya, “Effect of Fringing Fields on Subthreshold Surface Potential of Channel Engineered Short Channel MOSFETs,” in Proc. TENCON 2008 – IEEE Region 10 Conf., 19-21 November, 2008, doi: 10.1109/TENCON.2008.4766741
  63. S. Baishya, A. Mallik, and C. K. Sarkar, “A Two-Dimensional Surface Potential Based Subthreshold-Slope Model for Short-Channel MOS Transistors,” in Proc. 26th Int. Conf. on Microelectronics (MIEL), NIS, Serbia, 11-14 May, 2008, doi: 10.1109/ICMEL.2008.4559328
  64. S. Baishya, A. Mallik, and C. K. Sarkar, “A Threshold Voltage Model for DMG-MOS Transistors Taking into Account the Varying Depth of Channel Depletion Layers Around the Source and Drain,” in Proc. 2nd Int. Conf. on Industrial and Information Systems (ICIIS), Peradeniya, Srilanka, 2007, pp. 541 – 546, doi: 10.1109/ICIINFS.2007.4579236
  65. S. Chakraborty, S. Baishya, A. Mallik, and C. K. Sarkar, “Performance Evaluation of Analog Circuits With Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation,” in Proc. 1st Int. Conf. on Industrial and Information Systems (ICIIS), Peradeniya, Srilanka, 2006, pp. 99–102, doi: 10.1109/ICIIS.2006.365644
  66. S. Baishya, A. Mallik, and C. K. Sarkar, “A Subthreshold Drain Current Model for Deep Sub-micron MOSFETs,” Proceedings of the International Conference on Electronic and Photonic Materials, Devices and System (EPMDS), Kolkata, India, pp. E16–E18, January 2006.
  67. S. Baishya, A. Mallik, and C. K. Sarkar, “A Subthreshold Drain Current Model for Deep Submicron Pocket Implanted MOSFETs,” in Proc. Int. Semiconductor Device Research Symposium (ISDRS), Maryland, USA, 2005, pp. 360–361, doi: 10.1109/ISDRS.2005.1596135
  68. A. Mahanta and S. Baishya, “A SIMD/MIMD-organized General-purpose Systolic Array,” in Proc. of the Fifth International Conference on Signal Processing Applications and Technology, Dallas, USA, 1994, pp. 1295–1300

BOOKS/CHAPTERS

  1. Design of 5.5 GHz Highly Linear CMOS Low Noise Amplifier- Lambert Academic Publishing, 2013 (ISBN No- 978-3-659-49593-9), Co-author- Ram Kumar
  2. R. H. Laskar, F. A. Talukdar, R. B. Bhattacharjee, and S. Das, “Voice Conversion by Mapping the Spectral and Prosodic Features Using Support Vector Machine” Chapter contributed on the book entitled ‘Applications of Soft Computing- From Theory to Praxis’ Edited by Jörn Mehnen, Mario Köppen, Ashraf Saad and Ashutosh Tiwari, Springer Verlag, Vol-58, September 2009 [pgs 519-28]
  3. J. Rani, R. Kumar, F. A. Talukdar, and N. Dey, Contributed a chapter on “MRI Brain Tumor Segmentation using Fuzzy C- Means Technique- A Study,” in the title Recent Advances in Applied Thermal Imaging for Industrial Applications, IGI Global, 2017.
  4. R. Kumar, S. Rani, A. Sarkar and F. A. Talukdar “GPU Accelerated Level Set Method for MRI Brain Tumor Segmentation using Modified Probabilistic Clustering”, Classification and Clustering in Biomedical Signal Processing (IGI Global), Chapter 5, DOI: 10.4018/978-1-5225-0140-4, 2016
  5. K. Dharavath, F. A. Talukdar, R. H. Laskar, and N. Dey, “Face Recognition under Dry and Wet Face Conditions”, Intelligent Techniques in Signal Processing for Multimedia Security, Chapter: 17, Publisher: Springer SCI series, 2016
  6. J. Rani, R. Kumar, F. A. Talukdar, and N. Dey, “A Study on Various Image Processing Techniques and Hardware Implementation using Xilinx System Generator, Chapter-22 in Handbook of Research on Applied Video Processing and Mining, IGI Global, 2016
  7. Ram Kumar, Jayendra Kumar, F.A Talukdar, Nilanjan Dey, Amira Ashour and Fuqian Shi, ‘Design of High Gain LNA for Wireless Frontend Communication’, in Smart Trends in Information Technology and Computer Communications, Springer, pp. 102-110, https://doi.org/10.1007/978-981-13-1423-0_12

PROFESSIONAL MEMBERSHIPS

  • IEEE
  • IEEE Electron Device Society

AWARDS & RECOGNITIONS

  • ***

ADMINISTRATIVE RESPONSIBILITIES

  • Dean (Academic)
  • Dean (Research & Consultancy)
  • Head of the Department
  • Faculty Adviser (Central Library)
  • Associate Dean (Academic & Admission)

Ph.D. Scholars Guided

  1. Santosh Kr. Gupta, Thesis Title: Modeling and Simulation of Multi-Gate Multi-Material Transistors, 2013
  2. Brinda Shome (Bhowmick), Thesis Title: Modeling and Simulation of Hetero-gate Dielectric Tunnel FET Structures and Their Mixed-mode Applications, 2014
  3. Niladri Pratap Maity, Thesis Title: Tunneling Current and Interface Charge Densities in Ultra-Thin High-k Dielectric Materials Based MOS Devices, 2015
  4. Wasim Arif, Thesis Title: Investigation and modeling of spectrum sensing and mobility issues in cognitive radio, 2015
  5. Reshmi Maity, Thesis Title: Modeling and Simulation of Capacitive Micromachined Ultrasonic Transducers, 2015
  6. Koushik Guha, Thesis Title: Design and Modeling of RF MEMS Shunt Switch, 2015
  7. Sweta Chander, Thesis Title: Investigation of Heterojunction Silicon-on-Insulator Tunnel Field Effect Transistor in Nanometer Era, 2016
  8. Richik Kashyap, “Distributed Parameter Modeling and Autonomous Charge Extraction of d31 and d33 Mode Piezoelectric Energy Harvesters,” 2016
  9. Achinta Baidya, Thesis Title: Circuit Performance Analysis of Double Gate Junctionless Transistor with High-k Dielectrics and Metal Gates, 2017
  10. Rajesh Saha, Thesis Title: Modeling and Simulation of Electrical Parameters in FinFET Structures and the Effects of Statistical Variability of Metal Gate Workfunction, 2018
  11. Rajashree Das, “Channel and Gate Engineered Homo-Hetero Dielectric BOX FinFETs: Simulation, Modeling, and Applications,” 2018
  12. Sanjoy Debnath, “Study and Development of Algorithms towards Optimal Network Planning and Resource Allocation in Disaster Communication,” 2021

M.Tech. Scholars Guided

  1. Kalyan Koley, “SUBTHRESHOLD MODELING OF THE EDGE & FRINGING EFFECTS ON MOS TRANSISTOR,” 2009
  2. V. RAMANJANEYULU, “Optimization Consideration of Undoped Raised Source/Drain FinFET with effective SCE Control,” 2010
  3. Satyanand Namana, “Subthreshold Modeling of the Edge Effect on DG-MOS Transistor,” 2010
  4. Rajsekhar Kar, “Optimization of Hetero-material Gate Tunnel Source (PNPN) MOSFET,” 2011
  5. Victor Pal, Ultra Thin Body Partial SOI MOSFET with Suppressed Floating Body Effect,” 2011
  6. Janhavi Sen, Optimization and Length Scaling of Tunnel FET,” 2011
  7. Samrat Deb Choudhury, “Design and simulation of MEMS based comb-type, inter-digitated capacitive accelerometer,” 2012
  8. Banriskhem K. Khonglah, “Back Gate Engineering for Fully Depleted Silicon on Insulator Transistors with Thin Burried Oxide for Short Channel Effect Suppression and Improved Device performance,” 2012
  9. Pragati Singh, “Reduction of Gate Leakage Current through Ultra Thin Gate oxide using High-K Dielectrics,” 2013
  10. Richik Kashyap, “Design and Analysis of MEMS based Suspended-Gate MOSFET,” 2013
  11. Om Prakash Mahto, “A Novel SB-MOSFET with record Switching Characteristic,” 2014
  12. Rahul Sharma, “UTBB FDSOI technology and its Threshold Voltage Modulation for Low Power-High Speed Device,” 2014
  13. Soumen Deb, “Modeling and Simulation of a Novel 24-nm Asymmetric DMIDG MOSFET for Low Power Application,” 2014
  14. Saurabh Agarwal, “Design, Modeling and Simulation of RF MEMS Fixed-fixed Shunt Capacitive Switch,” 2015
  15. Gunturi Praveen, “Comparative Study between QFinFET and Trigate FinFET and Threshold Voltage Modeling of Heterojunction Tunnel FinFET with Source Overlap,” 2016
  16. Pankaj Kumar, “Investigation of group IV based Heterojunction Tunnel FinFETs,” 2017
  17. Debarun Borthakur, “High Precision Lumped Parameter Model for Piezoelectric Energy Harvesters,” 2017
  18. Vikas Kumar, “Simulation Study of Hetero Dielectric Gate All Around TFET and VErtical Super Thin Body FET,” 2018
  19. Ravindra Kumar Mourya, “Analysis of Hetero Dielectric Dual Gate TFET and Low Dropout (LDO) Linear Regulator,” 2019
  20. D. Mani Sankara Reddy, “Routing Optimization of VLSI Layout for Delay Reduction,” 2020
  21. Nirupam Sharma, “Design, Modelling and Development of Surface Accustic Wave (SAW) Band Filter with Center Frequency at 21.4 MHz,” 2020
  22. Aparajita Modak, “Derivation of the I-V Characteristics of a Coaxial Gate Carbon Nanotube Field Effect Transistor Focusing on NEGF Formalism and NATORi’S Model for Ballistic MOS,” 2021