Dr. Dipjyoti Das

Assistant Professor

Department of Electronics and Communication Engineering

National Institute of Technology Silchar

Silchar, Assam-788010, India

Email: dipjyoti@ece@nits.ac.in

ACADEMIC QUALIFICATIONS

Ph.D.(Organic Light Emitting Diode) from IIT Guwahati (2018)

B.E.(Electronics & Telecomm. Engg.) from Assam Engineering College (2011)

SELECTED PUBLICATIONS

• D. Das et al, “Experimental demonstration and modeling of a ferroelectric gate stack with a tunnel dielectric insert for NAND applications,” Accepted, 2023 IEEE International Device Meeting (IEDM), (Selected as a highlight paper). 
• D. Das et al, “A Ge-channel ferroelectric field effect transistor with logic-compatible write voltage,” IEEE Electron Device Letters, 44, 257-260, 2023. 
• D. Das et al, “Ferroelectricity in CMOS-compatible hafnium oxides: Reviving the ferroelectric field-effect transistor technology,” IEEE Nanotechnology Magazine, 15, 20-32, 2021. 
• D. Das et al, “High-k HfxZr1-xO₂ ferroelectric insulator by utilizing high pressure anneal,” IEEE Transactions on Electron Devices, 67, 2489-2494, 2020. 
• D. Das et al, “Demonstration of high ferroelectricity (P~29 µC/cm2) in Zr Rich HfxZr1–xO2 Films,” IEEE Electron Device Letters, 41, 34-37, 2020. 
• “Insertion of dielectric interlayer: a new approach to enhance energy storage in HfₓZr1-xO₂ capacitors,” IEEE Electron Device Letters, 42, 331-334, 2021. 
• D. Das et al, “Influence of high-pressure annealing conditions on ferroelectric and interfacial properties of Zr-Rich HfₓZr₁₋ₓO₂. capacitors,” IEEE Transactions on Electron Devices, 68, 1996-2002, 2021. 
• D. Das et al, “Sub 5 Å-EOT HfₓZr1–xO2 for next-generation DRAM capacitors using morphotropic phase boundary and high-pressure (200 atm) annealing with rapid cooling process,” IEEE Transactions on Electron Devices, 69, 103-108, 2022. 

PROFESSIONAL ATTRIBUTES 

• Proficient in the principles and processes of semiconductor devices, with a comprehensive understanding of the underlying physics and engineering.
• Experienced in the fabrication and characterization of diverse semiconductor devices, including MOSFETs, FEFETs, MFM capacitors, and a range of organic optoelectronic devices such as OLEDs, OSCs, OTFTs, and OMDs.
• Skilled in various technical processes such as Atomic Layer Deposition (thermal & plasma), Sputtering, Oxidation, Thermal Evaporation, Lithography, Mask Aligning, Etching, Ashing, and Post Metallization Annealing.
• Experienced in a variety of electrical and material characterization techniques, including DC and AC electrical measurements, capacitance- voltage (C-V) measurements, polarization-hysteresis measurement (P-V, PUND, PUNP, P-E, PSM), luminance-voltage (L-V) measurements, impedance, AFM, GIXRD, XPS, SEM, ellipsometry, and more.
• 4 years of hands-on experience working in clean room environments at prestigious research institutions, including the Korea National NanoFab Center (NNFC) at KAIST in South Korea, Marcus and Pettit Cleanroom at Georgia Tech in the United States.
• Experienced in data analysis using MATLAB, ORIGIN.

PUBLICATION SUMMARY

| Citations: 840 | h-index: 19 | i-10 index: 26 |                                                

• International Peer Reviewed Journals: 33 Nos.
• International Conference: 8 Nos.
• Book Chapter: 1 Nos.                   

REVIEWER EXPERIENCE 

• IEEE Electron Device Letters
• IEEE Transactions on Electron Devices
• IEEE Journal of Electron Device Society
• Journal of Physics D
• Nano Convergence.

 MEMBERSHIP

• IEEE MEMBER

AWARDS AND DISTINCTIONS

• BK21+ Fellowship, South Korea. 2019 – 2020
• Senior Research Fellow, MHRD, Govt, of India. 2014 – 2017
• Junior Research Fellow, MHRD, Govt, of India. 2012 – 2014
• Certificate of Proficiency, Assam Higher Secondary Education Council, Assam. 2007
• Anundoram Borooah Award 2005, Govt. of Assam.    2005