Prof. (Mrs.) Brinda Bhowmick (Shome)

February 28, 2022 by Brinda Bhowmick
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Brinda

Professor

National Institute of Technology (NIT) Silchar

Department of Electronics and Communication Engineering

Silchar, Assam, 788010, India

Email: bbhowmick@ece.nits.ac.in

Phone: +91-9954806903

Date of Joining: 29/06/2007 ( in permanent post at NIT Silchar)

Academic Experience: 20 years

Personal Webpage: http://ec.nits.ac.in/brinda/

 

ACADEMIC QUALIFICATIONS

  • Ph.D. (2014)
  • M.Tech. (2004)
  • B.E. (Hons)(2001)

EXPERIENCE

  • July 2022 – till date : Professor, National Institute of Technology (NIT) Silchar, Assam, 788010, India
  • Jun 2018 – 5th July 2022: Associate Professor, National Institute of Technology (NIT)Silchar, Assam, 788010, India
  • Jun 2007 – Jun 2018: Assistant Professor (Permanent Post), National Institute of Technology (NIT) Silchar, Assam, 788010, India
  • Aug 2006 – Jun 2007: Lecturer under SMDP Project, National Institute of Technology (NIT) Silchar, Assam, 788010, India
  • Oct 2005 – Jul 2006: Adhoc Lecturer in ECE and EE Department, National Institute of Technology Silchar, Assam, 788010, India
  • Jul 2005- Sep 2005: Lecturer in EEE Department, TOCH Institute of Science and Technology, Arakkunnam, Kerala, 682314, India
  • Aug 2004 – Mar 2005: Lecturer in EEE Department, Sikkim Manipal Institute of Technology, Majitar, Sikkim, 737102, India

RESEARCH INTERESTS AND SPECIALIZATION

  • Semiconductor Devices Physics,
  • Modelling and Simulation of low power emerging semiconductor devices,
  • 2D materials, Group III-V materials, High-K gate dielectrics,
  • Analog circuits,
  • Application of semiconductor devices as Bio sensor, Light sensor, and Gas sensor.

BIOGRAPHICAL SKETCH

Brinda Bhowmick (Shome) did her B.E. in 2001 with first class honours (80.8%), M.Tech. in 2004 with first class distinction ( 86.6%), and Ph.D. degree in 2014 in Microelectronics area. She passed 10th exam (HSLC) in 1995 ( 83.4%) and 12th Exam (HSS) in 1997 (76%).

Currently, she is a Professor in Electronics and Communication Engineering Department of NIT Silchar since July 2022. She has 20 years teaching experience. She achieved Visvesvaraya Young Faculty Research Fellowship in January 2018 from MeitY Government of India. She has authored 127 SCI/ SCIE International Journal papers, 37 conference papers, 19 book chapters and published two patents and three patents are in granted status. She has authored one book in Cambridge Scholars publisher UK. Eleven Ph.D. scholars are awarded Ph.D. degree under her guidance and four are currently doing PhD under her guidance. She has completed her tenure of Associate Dean ( Faculty Welfare) from Jan 2021 to Jan 2023. Currently she is the Dean ( Academic) of National Institute of Technology since 25th Sept 2023.

Her research interest is simulation and modelling of various semiconductor devices like TFET, SBMOS, FINFET, Graphene FET, Tunnel diode including Group III-V materials, 2D materials, and their applications in analog and digital circuits and sensors.

PROJECT(S)

  1. Sir Visvesvaraya Young Faculty Research Fellowship Award by Ministry of Electronics and Information Technology (MeitY), GOI, 2017 -2020 Sep. (16 Lakhs for 2 Year 9 Months), Completed ( Role as PI)
  2. Hetero-Junction Tunnel FETs: Characterization, Modelling and Simulation of Electrical parameters, under CSIR, Extramural Research Division……….9.54 lakhs….. (2017-2020),Completed ( Role as CO-PI)
  3. IEDC 2017 Project: Heart Attack Detection and Response system, DST,  (2017-2018), Completed ( Role as PI)

PATENT(S)

  1. Indian Patent filed and Published ( Inventors: Rupam Goswami, Vivek Mate, D Borah, B Bhowmick) on SYSTEM, METHOD AND APPARATUS FOR GENERATING TRUE RANDOM NUMBER FOR IDENTIFICATION AND VERIFICATION :No.201731000942, dated 31/08/2018
  2. Indian patent filed and Published ( Inventors:Brinda Bhowmick, Rajesh Saha, Siddhartha Singh, Utkarsh Bhatt) on Portable system for fast detection of PQRS and T wave ECG signals, application no.201931027301 dated 8/7/2019 
  3. German patent Granted ( Inventors: Abinash Panda, Puspa Devi, Brinda Bhowmick )” A SYSTEM FOR DESIGNING A NOVEL HIGHLY SENSITIVE HYBRID SURFACE PLASMON RESONANCE (SPR) BIOSENSOR,” No.20202210074 in 2021
  4.  German patent Granted ( Inventors: Ravindra Kumar Maurya, Brinda Bhowmick, Rajesh Saha) Title: A System for Developing and Analyzing a Parameter of Bohm Quantum Potential (BQP) Device”  No.202022105580 in 2022.
  5. South African Patent Granted ( Inventors: Zohmingliana, Brinda Bhowmick, Bijit Choudhury) Title: A Device for Designing and Analysising Double Gate Dual Material Vetical Nano ribbon Graphene TFET,  No 2022/10999, 2022

PUBLICATIONS(JOURNALS/CONFERENCES)

International Journals

2024

1. K Nasani, B Bhowmick, P  P Devi, ” Dielectric Modulation based Investigation of Heterojunction Dual Gate Vertical TFET for Bio-molecule Detection, ” accepted in Materials Science & Engineering B , Dec 2024

2 Ravindra Kumar Maurya, Rajesh Saha, B Bhowmick, “Oxide and Ferro Layer Thickness Optimization of Negative Capacitance Junctionless VSTB FET to Improve Electrical and Thermal Noise Performance,” Materials Science and Engineering B, vol. 309, August 2024, https://doi.org/10.1016/j.mseb.2024.117626

3.Radhe G Debnath, B Bhowmick, A K Yadav, ” A Novel Dual-Gate Negative Capacitance TFET for Highly Sensitive Label Free Biosensing, ” Semiconductor Science and Technoogy, vol 39, issue 9, DOI 10.1088/1361-6641/ad6eb0 August 2024.

4. Zohmingliana, Bijit Choudhury, B Bhowmick,” Device and Circuit-Level Performance Evaluation of DG-GNR-DMG,” Micro and Nanostructures, July 2024, https://doi.org/10.1016/j.micrna.2024.207942

5. Ravindra Kumar Maurya, V Kumar, Rajesh Saha, B Bhowmick,” Impact of Source/Drain Lateral Straggle on GIDL Current of Low SS NCFinFET,” International Journal of Electronics, Oct 2024, https://doi.org/10.1080/00207217.2024.2408798

6. Zohmingliana, Bijit Choudhury, B Bhowmick,” Analytical Modeling of Drain Current for DG-Graphene Nanoribbon Vertical Tunnel FET,” Microelectronics journal,Vol.147, May 2024, 106194 https://doi.org/10.1016/j.mejo.2024.106194

7.  R sharma, R Saha, R Goswami, B Bhowmick,” Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs,” Physica Scripta, vol.99, no.7  202410.1088/1402-4896/ad562d

8. Ravindra Kumar Maurya, Rajesh Saha, B Bhowmick, “Effects of the Remnant Polarization on the Electrical Characteristics of Steeper Sub-threshold Swing Fe-GeFinFET,” Materials Science & Engineering B, Vol.303, May 2024, 117317March 2024, https://doi.org/10.1016/j.mseb.2024.117317

9. Ravindra K Maurya, R Debnath, R Saha, B Bhowmick, ” Enhanced Magnetic Field Sensing with MAGNC-FinFET: A Current Mode Hall Effect Approach,” IEEE Transactions on Nano Technology, Feb 2024,doi: 10.1109/TNANO.2024.3373035.

10.S Kumar, S Hoque, D Bharti, R Saha, B Bhowmick,”Investigation of optical parameters in Ge source SELBOX tunnel FET under visible spectrum,”Micro and Nanostructures 193, 207915, 2024.

11.D Kumar, R Chaudhary, R Mitharwal, B Bhowmick, R Saha,”Impact of self-heating on geometric variations in Nano-Ribbon FET: Analog/RF perspective,”Micro and Nanostructures, 207908,2024

12. Sirisha Meriga, B Bhowmick, “Robustness of Raised Buried Oxide Ferro Electric Tunnel FET in presence of Temperature and Traps and its Analog/RF performance,” Applied Physics A: material Science and Processing, Springer, vol. 130, 223, 2024. https://doi.org/10.1007/s00339-024-07357-2

13. George Mili, Zohmingliana, B Bhowmick, “Sensitivity analysis of a double source stack lateral TFET-based gas sensor,” ECS Journal of Solid State Science and Technology, Volume 13, Issue 2, id.027001, 10 pp. Feb 2024, DOI: 10.1149/2162-8777/ad228c

 14.K Nasani, B Bhowmick, P P Devi, “Impact of Noise and Interface Trap Charge Analysis of a Hetero-Junction Dual Gate Vertical TFET device,” Journal of Electronic Materials, Feb 2024 https://doi.org/10.1007/s11664-024-10927-y

15.Swapna Bharali, B Bhowmick, B Choudhury, ” Investigation of Hetero Gate Oxide Hetero Stacked Triple Metal Vertical Tunnel FET with Variable Interface Trap Charges and Temperature,” Microelectronics Journal, Vol.143, January 2024, 106054,https://doi.org/10.1016/j.mejo.2023.106054.

16. K Vanlalawmpuia, P Ghosh, B Bhowmick, ” Insights into the Impact of Random Dopant Fluctuation on Ferroelectric Germanium source Vertical TFET,” Materials science & Engineering B, Volume 299, January 2024, 116994,doi.org/10.1016/j.mseb.2023.116994

17. N Niranjan, P Sarkar, BBhowmick, M Choudhury, K L Baishnab, “2-D Si0.8Ge0.2 source double-gate pocket PTFET for low power application: Modeling and simulation, “Materials Science and Engineering B, Vol 303, March 2024, 117290. doi.org/10.1016/j.mseb.2024.117290

2023

  1. Sirisha Meriga, B Bhowmick, Deep insight into Raised Buried Oxide SOI-Fe TFET and it’s Analog/RF and linearity Performance Parameters,” Transactions on Electrical and Electronic Materials, Sept 2023. doi.org/10.1007/s42341-023-00480-6
  2. Zohmingliana, Bijit Choudhury, B Bhowmick, ” “Design of Dual-band Rectifier Circuit for RF Energy Harvesting using Double-Gate Graphene Nanoribbon (GNR) Vertical Tunnel FET,” IEEE Transactions on Consumer Electronics, doi: 10.1109/TCE.2023.3319168.( Quartile Q1), Sept 2023.
  3. B Das, B Bhowmick, ” Dielectrically modulated Ferroelectric-TFET (Ferro-TFET) based biosensors,” Materials Science and Engineering B, August 2023.Volume 298, December 2023, 116841,doi.org/10.1016/j.mseb.2023.116841 ( Quartile Q2 )
  4. Zohmingliana, Bijit Choudhury, B Bhowmick, ” Analysis of the Impact of Interface Trap Charges on the Analog/RF Performance of Graphene Nanoribbon Vertical Tunnel FET,” Journal of Electronic Materials, July 2023, doi. 10.1007/s11664-023-10615-3 (Quartile Q2)
  5. Ravindra Kumar Maurya, Vivek Kumar, R Saha, B Bhowmick, “Effect of Curie Temperature on Electrical Parameters of NC-FinFET and Digital Switching Application of NC-FinFET, ” Microelectronics Journal, vol.139, 105892,  Sept 2023, doi.org/10.1016/j.mejo.2023.105892( Quartile Q2)
  6. Sirisha Meriga, B Bhowmick, ” Compact Drain current model of Double gate raised buried oxide TFET for Integrated Circuit Application, ” Journal of Computational Electronics, June 2023 doi. 202310.1007/s10825-023-02077-x ( Quartile Q2)
  7. K Nasani, B Bhowmick, P P Devi, “Effect of Lateral Straggle parameter on Hetero Junction Dual Gate Vertical TFET, ” Microlectronics Journal, vol.138 , August 2023 . doi.org/10.1016/j.mejo.2023.105845 (Quartile Q2)
  8. K Baruah, B Bhowmick, S Baishya, ” An analytical Approach to study the impact of Traps on Ge-Source Double Gate PNPN TFET, ” IETE Journal of Research, June2023. doi.org/10.1080/03772063.2023.2217794. (Quartile Q2)
  9. R Saha, R Goswami, B.Bhowmick, S.Baishya, “Simulation study of n+ pocket step shape heterodielectric double gate tunnel FET for switching and biosensing applications,” Mateials Sicence and Engineering :B, vol.293, 2023. doi.10.1016/j.mseb.2023.116491 (Quartile Q1)
  10. Zohmingliana, B. Choudhury, B.Bhowimck, ” Sensitivity and Stability analysis of Double-Gate Graphene Nanoribbon Vertical Tunnel FET for different Gas Sensing,” ECS Journal of  Solid State Science and Technology, ( IOP Science), January 2023. doi 10.1149/2162-8777/acb56d (Quartile Q2)
  11. Sirisha Meriga, B .Bhowmick, ” Investigation of a dual gate pocket doped drain Engineered Tunnel FET and its reliability issues,” Applied Physics A: material Science and Processing, Springer, vol.129, issue 104, Jan 2023. doi.org/10.1007/s00339-023-06394-7 (Quartile Q2)
  12. Ravindra Kumar Maurya, R.Saha, B. Bhowmick, “Low to High-Frequency Noise Behavior Investigation of Steeper Sub-threshold Swing NC-GeFinFET,” Microelectronics Journal, vol.131 , Jan 2023. 10.1016/j.mejo.2022.105642 (Quartile Q2)

                                                                                                                                                                 2022

  1. Zohmingliana, B.Choudhury, B.Bhowmick,” Study the Impact of Graphene Channel over Conventional Silicon on DC/analog and RF performance of DG Dual-Material-Gate VTFET,”  Microelectronics Journal vol.128, Oct 2022, doi.org/10.1016/j.mejo.2022.105581 (Quartile Q2)
  2. B. Das, B Bhowmick, “Impact of traps on DC, analog/RF, and linearity performance of Ferro-TFET,”  Silicon, August 2022.doi.org/10.1007/s12633-022-02167-8. (Quartile Q2)
  3. P. Ghosh, B.Bhowmik,” Performance Enhancement of a FET Device with Ferroelectric Tunnel Junction and its Application as a Biosensor,”  Journal of Computational Electronics, vol.21,pp.1416-1424,  Sept 2022. doi.org/10.1007/s10825-022-01935-4  (Quartile Q2)
  4. P Kumar, B Bhowmick, “Recent Progress on Sensitivity Analysis of Schottky Field Effect transistor Based Biosensors” Silicon Journal, doi : 10.1007/s12633-022-01994-z, 2022. (Quartile Q2)
  5. P.Ghosh, B.Bhowmick, ” Study of variability induced by Random Dopant Fluctuation in Fe DS-SBTFET ,” Microelectronics Journal, May 2022, doi.org/10.1016/j.mejo.2022.105467. (Quartile Q2)
  6. K Vanlalawmpuia, S K Mitra, B Bhowmick, ” An Analytical Drain Current Model of Germanium Source Vertical Tunnel Field Effect Transistor,” Micro and Nano structures,, available online in March 2022.doi.org/10.1016/j.micrna.2022.207197
  7. K Vanlalawmpuia, BBhowmick, ” Interfacial Charge Analysis and Temperature Sensitivity of Germanium Source Vertical Tunnel FET with Delta-Doped Layer, ” Microelectronics Reliability, vol.131, April 2022.doi.org/10.1016/j.microrel.2022.114512  (Quartile Q2)
  8. V Devi, B.Bhowmick, PP Devi, “Detection of SARS-CoV-2 Using Dielectric Modulated TFET Based Biosensor,” in Journal of Materials Science: Materials in Electronics, March 2022, doi.org/10.1007/s10854-022-08020-3, Epub 2022 Mar 16. PMCID: PMC8926094. (Quartile Q2)
  9. N Kumar, P Sarkar, B.Bhowmick, M Choudhury, KL Baishnab, “Modeling and simulation of 2-D SixGe(1-x) source dual-gate pocket NTFET,” Micro and Nano structures, Elsevier in March 2022.doi.org/10.1016/j.micrna.2022.207237
  10. K Vanlalawmpuia and B. Bhowmick, “Analysis of Hetero-stacked Source TFET and Heterostructure Vertical TFET as Dielectrically Modulated Label-Free Biosensors,” in IEEE Sensors Journal, Volume: 22, Issue: 1, pp.939-947, Jan. 2022, doi: 10.1109/JSEN.2021.3128473. (Quartile Q1)

2021

  1. R Saha, R Goswami. B Bhowmick, S Baishya, ” Comprehensive Investigation on RF/Analog Parameters in Ferroelectric Tunnel FET,’ Semiconductor Science and Technology, Nov2021, doi10.1088/1361-6641/ac3dd4 (Quartile Q1)
  2. K Vanlalawmpuia, B Bhowmick,” Analysis of Temperature Dependent Effects on DC, Analog/RF and Linearity Parameters for a Delta Doped Heterojunction Vertical Tunnel FET,” Silicon Journal, Nov.2021,doi 10.1007/s12633-021-01504-7
  3. R Saha, B Bhowmick, S Baishya, ” DC and RF/Analog Parameters in Ge-source SD-ZHP-TFET: Drain and Pocket Engineering Technique” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Oct 2021, doi 10.1002/jnm.2967
  4. R Kumar, B Bhowmick, ” Review of FinFET Devices and Perspective on Circuit Design Challenges,” Silicon Journal, Springer 2021, doi.10.1007/s12633-021-01366-z. (Quartile Q2)
  5. Saha, B.Bhowmick, S.Baishya,” Dependence of Lateral Straggle Parameter on DC, RF/Analog, and Linearity Performance in SOI FinFET” IETE Journal of Research (TIJR), sept 2021, doi10.1080/03772063.2021.1973915
  6. V Devi, B Bhowmick, P Devi,” Noise Behavior of Vertical Tunnel FETs under the Influence of Interface Trap States ,” Microelectronics Journal , Aug 2021, DOI:10.1016/J.MEJO.2021.105124. (Quartile Q2)
  7. R Saha,BBhowmick,S Baishya ,”Hot Carrier Effect in Ferro-FinFET for variation in temperature, work function, and FE layer thickness,” Integrated Ferroelectrics,Vol.221,Issue1, Dec. 2021, doi 10.1080/10584587.2021.1965842
  8. R Saha, B Bhowmick, S Baishya, “Study on Impact of Ferroelectric Layer Thickness on RF/Analog and Linearity Parameters in Ferroelectric-FinFET,” in International Journal of RF and Microwave Computer-Aided Engineering ,April 2021, doi.org/10.1002/mmce.22704
  9. V Devi, B Bhowmick,P Devi,” Linearity Performance and Intermodulation Distortion Analysis of D-MOS Vertical TFET,” in Applied Physics A, Springer,127, 340 ( April 2021). doi.org/10.1007/s00339-021-04496-8. (Quartile Q2)
  10. P Ghosh,B Bhowmick,” An Analytical Model of surface potential and capacitance in Heterojunction SELBOX TFET,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields,Wiley, in April 2021, doi10.1002/jnm.2887
  11. Vanlalawmpuia, B Bhowmick, ” Study on Induced Work-Function Variation of Titanium metal gate on various electrical parameters for Delta-doped layer Germanium Source vertical Tunnel FET” Journal of Computational Electronics, March 2021, doi10.1007/s10825-021-01686-8 (Quartile Q2)
  12. R Saha,R.Goswami, B Bhowmick and SBaishya,Analysis on Effect of Lateral Straggle on Analog, High Frequency and DC Parameters in Ge-source DMDG,”International Journal of RF and Microwave Computer-Aided Engineering,” Feb2021, doi.org/10.1002/mmce.22579
  13. .Kumar, P., Vinod, A., Dharavath, K,Brinda Bhowmick, “Analysis and Simulation of Schottky Tunneling Using Schottky Barrier FET with 2-D Analytical Modeling,” Silicon (2021). https://doi.org/10.1007/s12633-020-00879-3. (Quartile Q2)

2020

  1. B Das, B.Bhowmick, ” Effect of Curie Temperature on Ferro electric Tunnel FET and its RF/analog performance,” in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control,Oct 2020,doi: 10.1109/TUFFC.2020.3033761. ( Quartile Q1)
  2. V Devi, B Bhowmick, P P Devi,”Investigation of N+ Pocket Doped Junctionless Vertical TFET and its Digital Inverter Application in the Presence of True Noises,” in Applied Physics A, Springer,Sept 2020,doi.org/10.1007/s00339-020-03983-8. (Quartile Q2)
  3. V Devi, B .Bhowmick, PP Devi, ” Investigation of Temperature Variation and Interface Trap Charges in Dual MOSCAP TFET,” in Silicon ( Springer), Aug 2020,doi.org/10.1007/s12633-020-00651-7. (Quartile Q2)
  4. Saha, B.Bhowmick, S. Baishya, “Impact of Work Function on Analog/RF and Linearity Parameters in Step-FinFET,” Indian Journal of Physics July 2020,doi10.1007/s12648-020-01895-0
  5. K Vanlalawmpuia, R Saha, B.Bhowmick,” Study of effect of oxide thickness variation on electrical parameters and high frequency characteristic induced by work-function variation for delta-doped Germanium source vertical TFET,” in Semiconductor Science and Technology, IOP Science( Imapact factor 2.6), vol.35 2020 ( July).doi.org/10.1088/1361-6641/aba823
  6. P Ghosh,B.Bhowmick,” Investigation of Electrical Characteristics in a Ferroelectric L-patterned Gate Dual Tunnel Diode TFET,” in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, June 2020,doi10.1109/TUFFC.2020.2999826.( Quartile Q1)
  7. R Saha, R.Goswami,B.Bhowmick,S.Baishya,”Dependence of RF/Analog and Linearity Figure of Merits on Temperature in Ferroelectric FinFET: A Simulation Study,” in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, 2020 June,doi10.1109/TUFFC.2020.2999518. ( Quartile Q1)
  8. .R.Saha,S.Baishya,B.Bhowmick,”Dependence of Metal Gate Work Function Variation for Various Ferroelectric Thickness on Electrical Parameters in NC-FinFET,” FERROELECTRICS Vol 570, Issue 1, pp.67-76 (Taylor and Francis) 2021,doi.org/10.1080/00150193.2020.1839256
  9. P Ghosh, A. Roy, & B. Bhowmick ” The impact of donor/acceptor types of interface traps on selective buried oxide TFET characteristics” Appl. Phys. A,vol. 126, 330 (2020). https://doi.org/10.1007/s00339-020-03505-6. (Quartile Q2)
  10. V Devi, B.Bhowmick, P Puspa Devi “Modeling and Simulation of Optically Gated TFET for Near Infra-red Sensing Applications and its Low-Frequency Noise Analysis” IEEE Sensors Journal, 2020, doi10.1109/JSEN.2020.2991406, May, 2020. (Quartile Q1)
  11. V Devi, B.Bhowmick, P Puspa Devi “Investigation of dual MOSCAP TFET with improved vertical tunneling and its near infra-red sensing application” Semiconductor Science and Technology (IOP Science), vol.35, May2020,doi10.1088/1361-6144/ab8127
  12. P Ghosh, B.Bhowmick, “Effect of temperature in Selective Buried Oxide TFET in the presence of trap and its RF analysis” International Journal of RF and Microwave Computer-Aided Engineering., April 2020,DOI: 10.1002/mmce.22269
  13. V Devi, B. Bhowmick, P Devi,”N+ Pocket Doped Vertical TFET for Enhanced Sensitivity in Biosensing Applications: Modeling and Simulation ” in IEEE Transactions on Electron Devices, vol. 67, no. 5, pp. 2133-2139, May 2020.doi10.1109/TED.2020.2981303 (Quartile Q1)
  14. K Vanlalawmpuia, B.Bhowmick,”Investigation of Interface Trap Charges and Temperature Variation in Heterostacked-TFET” Indian Journal of Physics, Sept 2020 doi 10.1007/s12648-020-01834-z
  15. R Das, B Bhowmick, S Baishya,”Robustness to Ambipolarity and Improvement to HF FOMs of Dual Stacked Gate Dielectrics Underlap Heterojunction-TFETs” Indian Journal of Physics, Aug,2020 doi.10.1007/s12648-020-01821-4
  16. P Ghosh, B Bhowmick,” Deep insight into material-dependent DC performance of Fe DS-SBTFET and its noise analysis in the presence of interface traps,” AEU- International Journal of Electronics and Communications, vol.117 , April 2020,doi10.1016/j.aeue.2020.153124
  17. K Vanlalawmuia, B.bhowmick,” Optimization of a Hetero-structure Vertical Tunnel FET for enhanced Electrical Performance and effects of temperature variation on RF/linearity Parameters,” Silicon (Springer), Feb 2020.doi10.1007/s12633-020-00411-7. (Quartile Q2)
  18. .R.Saha, B.Bhowmick, S.Baishya”Impact of Lateral Straggle on Linearity Performance in Gate Modulated (GM) TFET” in Applied physics A,Material Science and Processing Volume :126 / 1-4 / 2020, 2020.doi10.1007/s00339-020-3373-3. (Quartile Q2)
  19. V Devi, B.Bhowmick, P Devi,”N+ Pocket Doped Vertical TFET Based Dielectric-Modulated Biosensor Considering Non-Ideal Hybridization Issue: A Simulation Study,” IEEE Transactions on Nano Technology,vol.19, pp.156-162, Feb 2020,doi 10.1109/TNANO.2020.2969206. (Quartile Q2)
  20. P Ghosh, B,Bhowmick “Optimization of Ferroelectric SELBOX TFET and Ferroelectric SOI TFET” ECS Journal of Solid State Science and Technology, Volume 9, Number 2, IOP science, Jan 2020 . (Quartile Q2)
  21. B Das, B.Bhowmick,” Noise behavior of Ferro electric Tunnel FET,” Microelectronics journal,Feb 2020, Vol.96. 2020 Doi.10.1016/j.mejo.2019.104677. (Quartile Q2)

  2019

  1. S Choudhury, K L Baishnab, B.Bhowmick,”An Evolutionary Algorithm based Optimized Double gate Hetero-material Tunnel FET,” Journal of Computational Electronics,Nov. 2019 https://doi.org/10.1007/s10825-019-01426-z. (Quartile Q2)
  2. P Ghosh,B.Bhowmick,”Analysis of Kink Reduction and reliability issues in Low-voltage Dual Tunnel Diode based SOI TFET,” Micro & Nano letters (IET), vol.15, Nov 2019 10.1049/mnl.2019.0427 
  3. RGoswami, B.Bhowmick, R. Khosla,”RF analysis and temperature characterisation of pocket doped L-shaped gate Tunnel FET,’ Applied Physics A, 2019 Sept, doi10.1007/s00339-019-3032-8. (Quartile Q2)
  4. P Ghosh,B.Bhowmick,R. Goswami, “Optimization of Ferroelectric Tunnel Junction TFET in presence of temperature and its RF analysis,” Microelectronics journal, vol.92, Sept’ 2019.doi.org/10.1016/j.mejo.2019.104618 (Quartile Q2)
  5. K Vanlalawmpuia, B.Bhowmick,” Investigation of a Ge-source vertical TFET with delta-doped layer” accepted in IEEE Transaction on Electron Devices, Aug 2019 doi10.1109/TED.2019.2933313 (Quartile Q1)
  6. P Ghosh, B.Bhowmick,” Reduction of kink effect in SELBOX Tunnel FET and its RF/Analog performance” Journal of Computational Electronics, July 2019 . Doi:010.1007/s10825-019-01382-8 (Quartile Q2)
  7. R Goswami, B.Bhowmick ” Comparative Analyses of Circular Gate TFET and Heterojunction TFET for Dielectric-Modulated Label-Free Biosensing’ IEEE Sensors Journal, July 2019, Doi10.1109/JSEN.2019.2928182. (Quartile Q1)
  8. P Ghosh, B.Bhowmick, ” Effect of temperature on reliability issues of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET)” Silicon (Springer) in June 2018.Doi.10.1007/s1263.(Quartile Q2)
  9. K Vanlalawmpuia, B.Bhowmick, “Linearity performance analysis due to lateral straggle variation in Hetero-stacked TFET” Silicon, Springer, May2019.Doi.10.1007/s12633-019-00189-3. (Quartile Q2)
  10. A Vinod, P. Kumar, B.Bhowmick,” Impact of Ferroelectric on the Electrical Characteristics of Silicon–Germanium based heterojunction Schottky Barrier FET” International Journal of Electronics and Communications,May 2019.Doi.10.1016/j.aeue.2019.05.030
  11. P Kumar, B. Bhowmick,”Source-Drain Junction Engineering Schottky Barrier MOSFETs and their Mixed Mode application,” Silicon Journal, April 2019.doi.10.1007/s12633-019-00170-0 (Quartile Q2)
  12. R Saha, B.Bhowmick, S.Baishya, “Impact of WFV on Electrical Parameters due to High-k/Metal Gate in SiGe Channel Tunnel FET,” Microelectronic Engineering, vol.214, issue C, pp. 1-4, June 2019, doi.org/10.1016/j.mee.2019.04.024
  13. R Goswami, B.Bhowmick, “Optimization of Electrical parameters of pocket doped SOI TFET with L shaped Gate,” Silicon Journal in April 2019.DOI: 10.1007/s12633-019-00169-7  (Quartile Q2)
  14. R Saha, B.Bhowmick, S.Baishya,”Impact of Mole Fractions due to Work Function Variability (WFV) of Metal Gate on Electrical Parameters in strained SOI-FinFET” Silicon (Springer), April 2019.doi 10.1007/s12633-019-00163-z  (Quartile Q2)
  15. V Devi, B.Bhowmick, P Devi, “Near-infrared optical sensor based on band-to-band tunnel FET” Applied Physics A (springer) , vol.125, April 2019.Doi10.1007/s00339-019-2636-3    (Quartile Q2)
  16. P Ghosh, B. Bhowmick,” Noise behaviour of δp+ Si1-xGex layer SELBOX TFET” Indian Journal of Physics, (Springer) May 2019, doi10.1007/s12648-019-01485-9..
  17. P Ghosh, B.Bhowmick, ” Optimization of electrical parameters in Fe DS-SBTFET and its application as a digital inverter” International Journal of Electronics, Taylor and Francis, April 2019. https://doi.org/10.1080/00207217.2019.1600744
  18. S K Mitra, B Bhowmick, ” An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET” Silicon (Springer), March 2019, doi.org/10.1007/s12633-019-0090-7   (Quartile Q2)
  19. S K Mitra, B Bhowmick, “Impact of Interface Traps on Performance of Gate-on-Source/Channel SOI TFET” Microelectronics Reliability (Elsevier), 2019, /doi.org/10.1016/j.microrel.2019.01.004
  20. R Saha, B.Bhowmick, S.Baishya, ” Analytical Threshold Voltage and Subthreshold Swing model for TMG FinFET” International Journal of Electronics, Taylor and Francis , vol.106, No.4, pp. 553-566, 2019,10.1080/00207217.2018.1545258

2018

  1. Saha, B.Bhowmick, S.Baishya, “Deep insights into electrical parameters due to metal gate WFV for different gate oxide thickness in Si step FinFET,” in Micro Nano letters, 2018,doi.org/10.1049/mnl.2018.5220
  2. P Ghosh, B.Bhowmick, “Low frequency Noise analysis of Heterojunction SELBOX TFET,” Applied Physics A material science & processing, Springer, Nov2018,DOI: 10.1007/s00339-018-2264-3   (Quartile Q2)
  3. Saha, B.Bhowmick, S.Baishya” Quantum Modeling of Threshold Voltage in Ge Dual Material Gate (DMG) FinFET” in Solid State Electronics, https://doi.org/10.1016/j.sse.2019.03.047, March 2019
  4. R Saha, K Vanlalawmpuia, B.Bhowmick, S.Baishya,” Deep Insight into DC, RF/Analog, and Digital Inverter Performance Due to Variation in Straggle Parameter for Gate Modulated TFET,”Materials Science in Semiconductor Processing, Vol.91, pp102-107doi.org/10.1016/j.mssp.2018.11.011
  5. P Kumar, B.Bhowmick, “Comparative analysis of hetero gate dielectric hetero structure Tunnel FET and Schottky barrier FET with n+ pocket doping for Suppression of Ambipolar conduction and improved RF/linearity performances” Journal of Nano Opto Electronics,Vol. 14, Number 2, February 2019, pp. 261-271(11)DOI: https://doi.org/10.1166/jno.2019.2488
  6. K Vanlalawmpuia, B.Bhowmick, M.Choudhury, “Optimization of fully depleted SiGe channel with raised source/drain buried oxide nMOSFET”, in International Journal of Nano particles, Sept 2018
  7. V Devi, B.Bhowmick, “Optimization of Pocket doped Junctionless TFET and its Application in digital Inverter, ” IET Micro Nano letters, Sept, 2018, doi: 10.1049/mnl.2018.5086
  8. K Vanlalawmpuia, R.Saha, B.Bhowmick, “Performance Evaluation of Heterostacked TFET for variation in lateral straggle and its application as digital inverter, Applied Physics A,Springer, Sept 2018,doi.org/10.1007/s00339-018-2121-4  (Quartile Q2)
  9. R Saha, B.Bhowmick, S.Baishya , ” Temperature Effect on RF/Analog and Linearity Parameters in DMG FinFET,” in Applied Physics A, Aug 2018 ,124(9) DOI: 10.1007/s00339-018-2068-5   (Quartile Q2)
  10. S K Mitra, B.Bhowmick, “A Compact Interband Tunneling Current Model of Gate-On-Source/Channel SOI-TFET” Journal of Computational Electronics (Springer), 2018. https://doi.org/10.1007/s10825-018-1236-3   (Quartile Q2)
  11. S K Mitra, B.Bhowmick, “A Physics Based Capacitance Model of Gate-on-Source/Channel SOI TFET”, IET Micro Nano letter in Aug, 2018, DOI: 10.1049/mnl.2018.5214.
  12. S K Mitra, B.Bhowmick, “Impact of Temperature and Fixed Oxide Charge Variation on Performance of Gate-on- Source/Channel SOI TFET and its Circuit Application”, Journal of Nano and Opto Electronics, 13, 1630–1640, 2018
  13. D Barah, A. singh, B.Bhowmick, “TFET on selective buried oxide (SELBOX) substrate with improved ION/IOFF ratio and reduced ambipolar current”, Silicon Journal, in May 2018. DOI: 10.1007/s12633-018-9894-0
  14. R Saha, B.Bhowmick, S.Baishya, “Effect of gate dielectric on electrical parameters due to metal gate WFV in n-channel Si step FinFET” , IET Micro Nano letters, DOI: 10.1049/mnl.2018.0189 , Online ISSN 1750-0443 Available online: 09 April 2018
  15. R Saha, B.Bhowmick, and S.Baishya,”Effect of Ge mole fraction on electrical parameters of Si1-xGex source step-FinFET and its application as an inverter”, Silicon, 10.1007/s12633-018-9846-8, 2018  (Quartile Q2)
  16. R Saha, B.Bhowmick, and S. Baishya ” Comparative Analysis among SMG, DMG, and TMG FinFETs: RF/Analog and Digital Inverter Performance” journal of Nano and Optoelectronics,DOIdoi:10.1166/jno.2018.2336, Vol. 13, pp. 1–9, 2018
  17. R Saha, B.Bhowmick, and S. Baishya, “Quantum Analytical Modeling of Inversion Charge and Threshold Voltage in Nanoscale Bi-Level Uniform Gate FinFET” ECS Journal of Solid State Science and Technology,vol.7, Issue 2,doi: 10.1149/2.0231802jss, 2018. (Quartile Q2)  
  18. P Kumar, B.Bhowmick,” Suppression of Ambipolar Conduction and Investigation of RF Performance Characteristics of Gate Drain Underlap SiGe Schottky Barrier Field Effect Transistor” Micro & Nano Letters, IET,DOI: 10.1049/mnl.2017.0895 , Online ISSN 1750-044, 2018.
  19. R.Saha, B.Bhowmick, S.Baishya, ” A 3D Statistical Simulation Study of Titanium Metal Gate WFV on Electrical Parameters in n-channel Ge step-FinFET,” Applied Physics A DOI: 10.1007/s00339-017-1545-6, 3. 2018  (Quartile Q2)
  20. P Kumar, B.Bhowmick”A Physics Based Threshold Voltage Model for Hetero – Dielectric Dual Material Gate Schottky Barrier MOSFET”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields.Wiley.10.1002/jnm.2320, 2018

2017

  1. R Goswami, B.Bhowmick “A Temperature Dependent Surface Potential Based Algorithm for Extraction of Threshold Voltage in Homojunction TFETs” International Journal of numerical modelling: Electronic network, devices and fields. DOI: 10.1002/jnm.2304. , 2017.
  2. R Saha, B.Bhowmick, and S. Baishya “3D Analytical Modeling of surface potential, threshold voltage, and subthreshold swing in Dual Material Gate (DMG) SOI FinFET”, Journal of Computational Electronics.DOI 10.1007/s10825 -017-1072-x.   (Quartile Q2)
  3. P Kumar, B.Bhowmick, “2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET,” vol.109, pp. 805-814, 2017 Superlattice and Microstructures, 10.1016/j.spmi.2017.06.001
  4. P Kumar, B.Bhowmick, “2-D Analytical modeling for electrostatic potential and threshold voltage of dual work function gate Schottky Barrier MOSFET” Journal of Computational Electronics, Springer, 2017.doi10.1007/s10825-017-1011-x  (Quartile Q2)
  5. R Saha B.Bhowmick, and S. Baishya , “GaAs SOI FinFET: Impact of Gate Dielectric on Electrical Parameters and Application as Digital Inverter”International Journal of Nanoparticles, 2018 Vol.10 No.1/2, pp.3 – 14, DOI: 10.1504/IJNP.2018.092668. 
  6. R Saha B.Bhowmick, and S. Baishya, “Si and Ge step-FinFETs: Work function variability, optimization and electrical parameters” Superlattice and Microstruc., Elsevier(2017), doi: 10.1016/j.spmi.2017.04.001.
  7. R. Goswami and B. Bhowmick, “An Analytical Model of Drain Current in a Nanoscale Circular Gate TFET,” in IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 45-51, Jan. 2017, doi: 10.1109/TED.2016.2631532. (Quartile Q1)
  8. R Saha, B.Bhowmick, and S. Baishya, “Statistical Dependence of Gate Metal Work Function on Various Electrical Parameters for an n-channel Si step-FinFET,” IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 969-976, March 2017. doi: 10.1109/TED.2017.2657233. (Quartile Q1)
  9. R. Goswami and B. Bhowmick, “An Algorithm for Extraction of Threshold Voltage in Heterojunction TFETs,” in IEEE Transactions on Nanotechnology, vol. 16, no. 1, pp. 90-93, Jan. 2017, doi: 10.1109/TNANO.2016.2628778. (Quartile Q2)

2016 and previous years

  1. .B.Bhowmick, R.Goswami, B.Das “A mathematical model and an algorithm for transmission in single rectangular potential barriers” International Journal of Pure and Applied Mathematics Volume 101 No. 5 2015, 605-615
  2. S K.Mitra, R.Goswami,B.Bhowmick “A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter”, Vol.92, pp 37-51, April 2016, Superlattices Microstructure,doi.org/10.1016/j.spmi.2016.01.040
  3.  B Bhowmick, S.Baishya “ Optimization and length Scaling of Raised Drain Buried Oxide SOI Tunnel FET,” Electronics letters,Vol. 49, Issue 16, 01 August 2013, p. 1031 – 1033, doi.10.1049/el.2013.1256
  4. R. Goswami, B.Bhowmick, S.Baishya “Electrical noise in circular gate TFET in presence of traps” Superlattices Microstruct, 86(2015) 342-354. (Elsevier)doi:10.1016/j.spmi.2015.07.064
  5. S Chander, B. Bhowmick, S. Baishya “Heterojunction fully depleted SOI-TFET with oxide/source overlap”, Superlattices Microstruct. 85 (2015) 45–50. (Elsevier) .doi:10.1016/j.spmi.2015.07.030
  6. B Das, R.Goswami, B.Bhowmick, “A Physics Based Potential and Electric Field Model of a Nanoscale Rectangular High-K Gate Dielectric HEMT,” Pramana Journal of physics, Pramana 11/2015; DOI: 10.1007/s12043-015-1100-y, March 2015. (Springer)
  7. R Goswami, B.Bhowmick, S.Baishya ‘Physics-based surface potential, electric field and drain current model of a ( ) Gate-Drain Underlap Nanoscale n-TFET,”International Journal of Electronics, vol.103, Issue 9, Feb 2016 ( Taylor & Francis).doi.org/10.1080/00207217.2016.1138514
  8. R Gowami, B.Bhowmick, S.Baishya “Effect of Scaling on Noise in Circular Gate TFET and its Application as a Digital Inverter,” vol.53, pp16-24, July 2016, Microelectronics journal. doi.org/10.1016/j.mejo.2016.04.009   (Quartile Q2)
  9. P Kumar, W. Arif, B.Bhowmick “Scaling of Dopant Segregation Schottky Barrier Using Metal Strip Buried Oxide MOSFET and its Comparison with Conventional Device,” Silicon Journal,2016, DOI 10.1007/s12633-016-9534-5, available online   (Quartile Q2)
  10. Rahin Pegu, Rupam Goswami, Brinda Bhowmick, Madhuchhanda Choudhury, ‘Optimization and modelling of Electrical Characteristics of 3D Gate all around Silicon nano wire MOSFET with tri-material gate and comparison with conventional MOSFET,” Discovery, 2015, 43(199), 158-162
  11. K Jena, B.Bhowmick, S.Baishya, “Simulation and Optimization of a partial gate all around Cylindrical Tunnel FET” International journal of recent trends and Technology, (ISSN: 2277 – 3878, Volume-2, Issue-5, pp.43-45, November 2013.
  12. B Bhowmick and S.Baishya “An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance,”International journal of VLSI design and Communication System , Vol.3, no.1,pp.1-11, Feb. 2012. DOI : 10.5121/vlsic.2012.3101
  13. B Bhowmick and S.Baishya “A Physics–based Model for Electrical Parameters of Double gate Hetero-material Nano Scale Tunnel FET,” International Journal of Applied Information Systems 1(3):25-32, February 2012. Published by Foundation of Computer Science and NASA, New York, USA
  14. B Bhowmick and S. Baishya “ Performance analysis of double hetero-gate tunnel field effect transistor,” ACEEE International Journal on Electrical and Power Engineering, Vol. 3(1), Feb. 2012. DOI: 03.EES.2011.1.513
  15. M Das, B.Bhowmick, “Effect of temperature on SiGe Heterogate Raised Buried Oxide Drain Tunnel FET Electrical Parameters”, Lecture Notes in Electrical Engineering, Springer, Vol. 150, 2013, pp. 283-291
  16. M K Suman, Sandeep Kumar, B.Bhowmick, “ A comparative study of ballistic DG nMOS for 9.8nm gate length with Mixed gate oxide over single gate oxide by DC and RF analysis, In International Journal of Innovative Research in Science, Engineering and Technology, vol.3, March 2014, pp.1403-1408
  17. B Bhowmick , S. Baishya “ Influence of Hetero-Material Gate Dielectric of Double Gate Tunnel FET on Electrical Characteristics,” International Journal of Wisdom Based Computing, Vol. 1 (3) , pp.28-31, December 2011

International Conferences

  1. K Nasani, B Bhowmick, P puspa Devi, “Study of Heterojunction Dual Gate Vertical TFET Applications in Gas Sensing, ” accepted in NUSOD 2024, New Delhi, 23rd to 26th Sept 2024.
  2. TVS Kranti, B Bhowmick, S Nath, “ CMOS 3 rd Order G m–C Lowpass Filter design for Electroencephalography  “IEEE International Conference on Smart Systems for applications in Electrical Sciences (ICSSES) , 3-4 May,DOI: 10.1109/ICSSES62373.2024    
  3. Zohmingliana, M. R. Tripathy, B. Choudhury, and B Bhowmick, ”Optimization of GrapheneNanoribbon Vertical Tunnel FET for amplify Electrical Performance, RF/Linearity Parameters, and its digital application,” Micro/Nanoelectronics Devices, Circuits and Systems, NIT Silchar, 29-31 Jan 2024.
  4. BV Rao, S Meriga, B Bhowmick, A Kumar, “DC and Analog/RF Performance Analysis of Hetero Buried Oxide (BOX)-Extended Source Tunnel FETs, accepted in Springer International Conference on Micro/Nanoelectronics Devices, Circuits and Systems (MNDCS-2024), 29-31 Jan 2024
  5. K Nasani, B.Bhowmick, P Puspa Devi, ” Study of parametric variations on Heterojunction Dual Gate Vertical TFET for performance Enhancement,”  Proceedings of IEEE SILCON 2023, 4th to 6th Nov, 2023 NIT Silchar
  6. R. K. Maurya, V. Kumar, R. Saha and B. Bhowmick, “Effects of Ferro-thickness and Temperature on Electrical Performance of Si:HfO2 based NC-FinFET,” 11th International Symposium on Electronic Systems Devices and Computing (ESDC), Sri City, India, 2023, pp. 1-6, doi: 10.1109/ESDC56251.2023.10149857.
  7. Zohmingliana, B. Choudhury, B Bhowmick, “Impact of Dual Gate Material on performance in Armchair Graphene Nanoribbon Vertical TFET of 1.35 nm Widths”, Springer International Conference on Micro/Nanoelectronics Devices, Circuits and Systems (MNDCS-2023), 29-31 Jan 2023.
  8. Sirisha Meriga and B. Bhowmick, ” Schrodinger Wave equation based Drain Current Model for Nano Scale device, ” IEEE  3rd Global Conference for Advancement in Technology (GCAT), Bangalore, Karnataka, India, 7 to 9th Oct, 2022. doi: 10.1109/GCAT55367.2022.9971920.
  9. V. D. Wangkheirakpam, B. Bhowmick and P. D. Pukhrambam, “Vertical Tunnel FET Technology: Optimization and Reliability Perspective,” 2021 International Conference on Computational Performance Evaluation (ComPE), 2021, pp. 820-825, doi: 10.1109/ComPE53109.2021.9752448. ( available online April 2022)
  10. R.Saha, R Goswami, B Bhowmick, S Baishya, “‘Implication of WFV in FinFET Due to Square and Right Angle Triangle Grain: A Comparative Study’ accepted for 16th IEEE Nanotechnology Materials and Devices Conference (IEEE NMDC 2021)
  11. V. D. Wangkheirakpam, B. Bhowmick and P. D. Pukhrambam, “Near Infra-red Photosensor using Optically Gated D-MOS Vertical TFET,” 2021 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD), 2021, pp. 47-48, doi: 10.1109/NUSOD52207.2021.9541496.
  12. R Saha, DK Panda, R Goswami, B Bhowmick, ” Effect of Drain Engineering on DC and RF Characteristics in Ge-source SD-ZHP-TFET” in proceedings of Devices for Integrated Circuit (DevIC), 2021,May 19-20, 2021, IEEE EDS Kolkata Chapter.
  13. U.Bag, B.Bhowmick,”Review of Emerging Tunnel FET Structures,” Proceedings of 2021 Springer International Conference on Micro/Nanoelectronics Devices, Circuits and Systems (MNDCS-2021), 29-31 Jan 2021.
  14. P.Ghosh, B.Bhowmick,” The Impact of Interface Traps (acceptor/donor) on Fe DS-SBTFET Characteristics,” proceedings of IEEE TENCON 17-19 Oct, Kochi Kerala,2019
  15. U Bhatt, S Singh, B Bhowmick “Portable System for Real Time Detection of P, QRS and T Waves from ECG Signals ” accepted in IEEE 5th I2CT 2019 Pune, India
  16. S. Kothapalli, U Pandey, B. Bhowmick, ” Optimisation of electrical characteristics of Tunnel FET incorporating Gate Engineering,” accepted in MOS AK India, IIT Hyderabad
  17. D. Bisharad, D. Dey, B. Bhowmick, ” Fast Detection of P,Q,S and T waves from Normal ECG signals using local context windows”, accpted in IEEE RCAR, Maldives, Aug1-5, 2018.
  18. Vikas Kumar, Rajesh Saha, Rajashree Das, BrindaBhowmick, Srimanta Baishya, “Comparison between Square and Right Angle Triangle Grain Due to WFV in Metal Gate and Implication of WFV in FinFET” NANOFILM 2017, 16-17 Nov, 2017, IEEE sponsored.
  19. V. Devi, B.Bhowmick, ” Optimization of N+ hetero pocket doped Dual metal Vertical TFET” proceedings of 2nd International Conference on Computing Methodologies and Communication (ICCMC 2018) , IEEE sponsored
  20. R.Saha, B.Bhowmick, S.Baishya, “Effects of Temperature on Electrical Parameters in GaAs SOI FinFET and Application as Digital Inverter” accepted in Devices for Integarted Circuits (DevIC 2017)”, Kalyani Government Engineering College, March 23-24, 2017.
  21. K.Vanlalawmpuia, M.Choudhury, B.Bhowmick “ Optimization of Electrical parameters in SiGe channel nMOS” accepted in Devices for Integarted Circuits (DevIC 2017)”, Kalyani Government Engineering College, March 23-24, 2017
  22. R.Goswami, B.Bhowmick “Circular Gate Tunnel FET: optimization and noise analysis” International Conference on Advances in Computing and Communications, Elsevier (ICACC-2016), Kerala.
  23. K.Kumar, A.Kumar, B.Bhowmick, “Field Plated High-k Gate Dielectric AlGaN/GaN HEMTs for Power Applications”, 3rd international conference on electronics and communication systems (icecs 2016),coimbatore, india.
  24. Prasant Singh, B.Bhowmick “Dual metal Dual dielectric based Tunnel FET With Underlap of Source and Gate” accepted in Research in Intelligent computing in Engineering, Nagpur, Mahastra,8-9th April,2016.
  25. S. K. Mitra, Rupam Goswami, and B. Bhowmick “Dual Buried Oxide SOI Hetero Dielectric TFET”, International Conference on Mathematical Computer Engineering – 2015 (ICMCE-2015), December, 2015, Chennai, India
  26. S. K. Mitra, Rupam Goswami, and B. Bhowmick “Dual Buried Oxide SOI Hetero Dielectric TFET”, International Conference on Mathematical Computer Engineering – 2015 (ICMCE-2015), December, 2015, Chennai, India
  27. S.Mitra, R.Goswami, B.Bhowmick “Optimization and Scaling of a SOI TFET with Back Gate Control“Proceedings of International Conference Recent Developments on Control, Automation and Power Engineering (IEEE), Noida, India , 12-13 March 2015.
  28. S.Mitra, R.Goswami, B.Bhowmick, “A Dual Dielectric Step-Gate SOI n-Tunnel FET,” Proceed. Of 2ndInternational Conference on Electrical, Electronics, Engineering Trends, Communication, Optimization and Sciences (E3COS),AP, India, 28th – 30th March-2015
  29. R.Goswami, B.Das, B.Bhowmick, S. Haque, “ A single gate nanoscale n-Channel Silicon MOSFET with gate overlap SiGe region for improved Ion/Ioff ratio,” Proceed. Of International Conference on Circuits, Power and Computing Technologies 2014 (IEEE), Kanyakumari, 20-21st March
  30. B.Bhowmick, K.Jena, and S.Baishya, “A Self-consistent model for hetero-Gate All Around Tunnel FET,” Proceed. Of International conference on Devices, Circuits and Systems, Coimbatore, 6-8th March, 2014(IEEE).
  31. R. Goswami, B.Bhowmick, “ Hetero-gate-dielectric gate-drain underlap nanoscale TFET with a δp+ Si1−xGex layer at source-channel tunnel junction,” Proceed. Of Green Computing Communication and Electrical Engineering (ICGCCEE) IEEE, 2014, 6-8th March, Coimbatore.
  32. B.Das, B.Bhowmick, “AlGaN/ GaN nanoscale HEMT with Arc shaped gate and stacked HfO2-SiO2 gate dielectric,” Proceed. Of Green Computing Communication and Electrical Engineering (ICGCCEE)IEEE, 2014 , 6-8th March, Coimbatore.
  33. B.Bhowmick, S.Baishya, R.Goswami, B.Das, and C.Joishy, “An Optimized SOI g-TFET and its application in a Half Adder Circuit,” Proceed. Of 2nd International Conference on Devices Circuits and systems (ICDCS’14), IEEE-EDS, Coimbatore, India, March 2014.
  34. B.Bhowmick, S. Baishya, and R.Kar “ Length scaling of Hetero Gate Dielectric SOI PNPN TFET,” Proceedings of INDICON (IEEE)2011, Hyderabad, 16th -18th Dec,2011
  35. B.Bhowmick ,S.Baishya, and J.Sen “ Capacitance measurement of a SOI tunnel FET,” Proceedings of the International Conference on Advances in Electrical Engineering, Dhaka, Bangladesh, pp. 264-267, December 2011
  36. B.Bhowmick, and S.Baishya “ Heterogate double gate dielectric tunnel FET with record high on/off current ratio,” Proceedings of the International Conference on VLSI, Commmunication and Instrumentation, Kottayam, India, pp.7-9, 7-9th April 2011
  37. B.Bhowmick, S.Baishya “ Mixed mode analysis of Raised Buried Oxide Tunnel FET,” Proceedings of International Conference World Congress on Engineering,WCE 2012,U.K, London,pp. 971-974, 4-6 July 2012.

BOOKS CHAPTERS

  1. K.Jena, B.Bhowmick,” Optimization of 3 dimensional tunnel fet and its digital applications” Lambert Academic publishing, Germany, November, 2014.
  2. B.Bhowmick, R.Goswami, ” Band gap modulated Tunnel FET” ,as book chapter in ” Field Effect Transistors – Materials, Fabrication and Application” Publisher: InTech – open science | open minds ( DOI: 10.5772/intechopen.76098)
  3. R.Goswami, B.Bhowmick, “DIELECTRIC MODULATED TFETs AS LABEL-FREE BIOSENSORS” as book chapter in ” Field Effect Transistors – Materials, Fabrication and Application” Publisher: InTech – open science | open minds ( doi.org/10.5772/intechopen.76000).
  4. B.Bhowmick, ” Design of a novel tunnel FETfor low-power applications” as BOOK chapter of IET Book Proposal VLSI and Post-CMOS Devices, Circuits and Modelling, Aug’2019. ..Book DOI: 10.1049/PBCS073F Chapter DOI: 10.1049/PBCS073F_ch
  5. U Pandey, K Guha, KL Baishnab, B.Bhowmick,” Ferroelectric FET as a Low-Power Device with Reduced SCEs and RDF Effect” in Lect. Notes Electrical Eng., Vol. 664.
  6. K Vanlalawmpuia,B Bhowmick, A novel vertical Tunnel FET and its application in mixed mode” book chapter for a Book entitled “Nanoelectronic Devices for Hardware/Software Security”, CRC Press, Taylor & Francis Group an international publisher of progressive academic research .eBook ISBN9781003126645
  7. R Saha, B Bhowmick, S Baishya,”RF/Analog and Linearity Performance Evaluation” Book chapter in Electrical and Electronic Devices, Circuits and Materials: Design and Applications, CRC press 2021…….eBook ISBN9781003097723
  8. V. Devi, B Bhowmick, P Devi, “Vertical Tunnel FET having Dual MOSCAP Geometry,” Sub-Micron Semiconductor Devices: Design and Applications”. CRC press, Taylor and Francis group,2022, eBook ISBN9781003126393
  9. S. Choudhury, K. L. Baishnab, B.Bhowmick, K. Guha “Hybrid intelligent technique based doping profile optimization in a double gate hetero-dielectric TFET.” Submicron semiconductor devices: design and applications, CRC Press Taylor and Francis Group, 2022,eBook ISBN9781003126393
  10. K Vanlalawmpuia, B Bhowmick ,” Lateral straggle and its impact on Hetero stacked source Tunnel FET” in “Contemporary Trends in Semiconductor Devices” by Springer Nature in 2022…….DOI: 10.1007/978-981-16-9124-9_8
  11. B.Das and B. Bhowmick, “Effect of Noise and Temperature on the Performance of Ferro-Tunnel FET,” Contemporary Trends in Semiconductor Devices, Springer Nature Pvt. Ltd. 2022 Print ISBN: 978-981-16-9123-2 Electronic ISBN: 978-981-16-9124-9
  12. P.Ghosh, B Bhowmick, “SELBOX TFET and DTD TFET for DC and RF/Analog Applications”,Contemporary Trends in Semiconductor Devices, Springer Nature Pvt. Ltd. 2022, Print ISBN: 978-981-16-9123-2 Electronic ISBN: 978-981-16-9124-9
  13. V Devi, B. Bhowmick, P Puspa Devi, ” Dielectric Modulated Biosensor Based on Vertical Tunnel Field Effect Transistor,” as book chapter Smart Innovation, Systems and Technologies, Springer series. 2022.vol 322. Springer, Singapore. https://doi.org/10.1007/978-981-19-7107-5_9
  14. S. Kothapalli, Zohmingliana, B Bhowmick, “Comparative Study of gate Engineered TFETs and Optimization of Ferroelectric Hetero Gate TFET structure, ” accepted chapter in Book Titled “Advanced Ultra-Low Power Metal Oxide Semiconductor Field Effect Transistors and their Application (Wiley Press)”.2022 August ( in press)
  15. K Lakshmi, B.Bhowmick, ” Dual Source Vertical Tunnel Field Effect Transistor : A simulation study” accepted as book chapter in “Nanoscale Field Effect Transistors: Emerging Applications” in Bentam book, web of science and Scopus indexed. 2022 September ( in press)
  16. S. Meriga, B Bhowmick, ” Optimization of Hetero buried Oxide Pocket doped Gate Engineered Tunnel FET Structure,” accepted as book chapter in Advanced Field Effect Transistor: Theory and Applications, CRC Press, 2023.
  17. B.Das, H. Borah, B.Bhowmick, “A detailed review on growth and evolution of TFET Biosensor for biosensing application,” book chapter in Handbook of Emerging Materials for Semiconductor Industry, Springer, 2024 Jan, doi10.1007/978-981-99-6649-3_43.
  18. V Devi, B. Bhowmick, P Puspa Devi, G Singh, ” OPTICALLY GATED VERTICAL TUNNEL FET FOR NEAR-INFRARED SENSING APPLICATION” Nanoelectronics Devices: Design, Materials, and Applications (Part 1), ISBN (Online): 978-981-5136-62-3, 2023
  19. S.Meriga, BBhowmick, ” Optimization of Hetero Buried Oxide Ferro TFET and its analysis,” accepted in book FeFET: Devices Trend, Technology and Applications to be published by Wiley and Scrivener an international publisher of progressive academic research,2024

BOOK

1. B.Bhowmick, R.Goswami, R.Saha, ” Simulation and Modelling of Emerging Devices: Tunnel FET and FINFET,” Cambridge Scholars Publishing, 2023, Lady Stephenson Library, Newcastle upon Tyne, United Kingdom, ISBN: 1-5275-0702-5 ISBN13: 978-1-5275-0702-9

 

AWARDS & RECOGNITIONS

  • GATE-EC 2002 Qualified (1530 All India Ranking in EC)
  • First Class First in B.E. (EE) from Regional Engineering College  Silchar in 2001
  • VIFA 2016 award  outstanding teacher winner
  • Sir Visvesvaraya Young Faculty Research Fellowship winner, MeitY Govt. of India
  • Reviewer of Many reputed SCI and SCIE journals like IEEE transaction on electron Device, ECS journal, Journal of Computational Electronics, IEEE sensors Journal, International Journal of Numerical Modelling, International Journal of Electronics, Physica Scripta, Silicon, IEEE Transactions on Nano Technology etc.
  • Resource person/Invited talks in various workshop/short term courses and chaired/ Co chaired many technical sessions

  • SPECIAL MERIT SCHOLARSHIP BASED ON STATE LEVEL EXAMINATION in 1995, Assam Government ( 10th exam, HSLC)

  • SPECIAL MERIT SCHOLARSHIP BASED ON STATE LEVEL EXAMINATION in 1997, Assam Government (12th exam, HS)

  •  4th POSITION IN SPECIAL MERIT SCHOLARSHIP EXAMINATION IN KARIMGANJ DISTRICT OF ASSAM in 1992, district level inspector of schools ( standard 7)

ADMINISTRATIVE RESPONSIBILITIES

  • Dean Academic ( From 25th Sept 2023 to till date)
  • Chairperson Purchase Committee of CCC ( from Oct 2022 to till date)
  • Associate Dean ( Faculty Welfare) from 13th  Jan 2021 – 17th Jan 2023
  • Member of Board of PG studies, Tripura University, 2023-2024
  • Member of Library ( Institute) Sub Committee; From 2010 to till date
  • Member of DPMC ECE Dept., March 2022 to till date
  • Chairman of IQAC, ECE Dept., March 2022 to till date
  • Member of NBA Committee, ECE Dept., March 2022 to till date
  • Coordinator of UGRC Research Projects , Dec 2020 to Feb 2024
  • Departmental Exam Coordinator, July 2015 to March 2018
  • Co-Coordinator of SMDP-II project, 2010 July -2013, March
  • Lab-in-charge of Basic Electronics (2010 July -2013 June)
  • Research Promotion Cell Incharge ,Oct, 2015 to Jan’ 2018
  • DPMC Sec.of ECE Dept., Oct 2018 to May 2020
  • Member of DUPC ECE Dept., May 2020 to Feb 2022
  • Internal Complaint Committee member, October 2015 to Sept 2018
  • Ass. Warden of GH-2, from Dec, 2010 – Dec, 2012
  • Coordinator Time Table Committee, From 2010 -2012

Ph.D. Scholars Guided

Awarded: 11

  1. Rupam Goswami: PhD degree awarded on 4th Dec’2017 ( As Sole guide), Title of thesis: Gate Engineered and Bandgap Engineered TFETs: simulation, modeling and application, ( working as Asst Professor in ECE Deptt. in Tezpur University)
  2. Rajesh Saha: PhD degree awarded on 15th June 2018 ( As Co-guide) Title of the thesis: Modeling and Simulation of Electrical Parameters in FINFET Structures and the Effects of Statistical Variability of Metal Gate Workfunction, ( worked as Assistant Professor in ECE In MNIT Jaipur and now in NIT Silchar ECE Dept)
  3. B Prashanth Kumar: PhD degree awarded on 5th Oct’2018 ( As Sole Guide) Title of thesis:Modeling, Simulation and Optimization of Hetero Junction Schottky Barrier FET and RF/linearity Performances for Low Power applications . ( working as Asst. Professor in VIT Chennai)
  4. Suman Kumar Mitra: (As Sole Guide) PhD degree awarded on 13th March ‘2019 : Thesis Title;Simulation, Modeling and Reliability issues of Gate-on-Source/Channel SOI TFET with Back Gate .( Working as Assistant Project under TEQIP in Harcourt Butler University in Kanpur upto Sept 2021, Now as Project Engineer Sanapse Design (A Quest Global Company) ..)
  5. Puja Ghosh: ( As Sole guide) PhD degree awarded on 12th April 2021:(Thesis Title: Bandgap Engineered Selective Buried Oxide Tunnel FETs: simulation, modeling and applications ),( Working as Assistant Professor in IIIT Ranchi in ECE Dept.)
  6. W. Vandana Devi : PhD degree awarded on 2nd March 2022 ( Main guide) (Performance Assessment of Vertical Tunnel FETs: from Theory to Sensing Applications) ( Working as Asst. Professor in MNNIT Allahabad till July 2023, Asst. Professor in NIT Delhi, currently Assistant Professor in NIT Manipur)
  7. K Vanlalawmpuia: (Sole guide) PhD degree awarded on 25th April 2022 (thesis Title : Simulation and Performance Analysis of Lateral and Vertical Tunnel FETs and their Biosensor Applications) : ( Working as Assistant Professor IIIT Nagpur till Ist week of July, Assistant professor in NIT Mizoram)
  8. Basab Das: (Sole guide) PhD degree awarded on 26th August 2022 ( Thesis Title: Simulation and Modelling of Gate-Engineered Tunnel FET ) : working as Assistant Professor GIMT Guwahati
  9.  Sirisha meriga: ( Sole Guide) PhD Degree awarded on 16th Oct 2024 ( Thesis Title: Design and Investigation of a Raised Buried Oxide SOI Ferro-electric Gate Tunnel
    FET) working as Assistant Professor in Andhra Pradesh
  10. Ravindra Kumar Maurya: ( Main Guide) PhD degree awarded on 4th Nov 2024 ( Thesis Title: Investigation on Electrical Parameters in Negative Capacitance (NC) FinFET and NC-JLVST FET: Simulation, Modeling, and Magnetic Sensing Application: working as Assistant Professor in  Veermata Jijabai Technological Institute ( VJTI) Maharashtra
  11.  Zohmingliana (Main guide) PhD degree awarded on 9th Dec 2024 ( Dual Material Double Gate Graphene Nanoribbon Vertical Tunnel FETs: Gas Sensor and Circuit Level Application). Working as Assistant Professor ( Adhoc) in Mizoram university.

 Currently Guiding: 04

  1. Swapna Bharali (Co Guide, part time, Progress I appeared)
  2. George Milli (Sole Guide, Progress seminar II appeared and Enhancement seminar appeared)
  3. Karthik Nasani (Main Guide, Progress seminar II and Enhancement seminar appeared)
  4.  Venkateswara Rao Busani ( Co Guide, QIP, Progress I appeared)

M.Tech. Scholars Guided

 Guided _ 26

  1. Jahnvi Sen: Optimization of Raised buried Oxide Tunnel FET (2010-2011)
  2. RajsekharKar: Optimization of hetero-material gate Tunnel Source (PNPN) MOSFET(2010-2011)
  1. Monalisa Das: A simulation study of SiGeheterogate raised buried oxide drain TunnelFET and analysis of the effect of temperature on electrical parameters. (2011-2012)
  2. KanjaLochan Jena: Optimization of 3D Tunnel FET and its digital application. ( 2012-2013)
  3. RupamGoswami: Gate-drain underlap nanoscale n-TFET with a δp+,si1-xGex Layer at source channel tunnel junction- simulation and modeling.(2013-2014)
  4. Basab Das: Simulation and Modelling of AlGaN/GaN high electron mobility transistor with gate dielectric. (2013-2014)
  5. Mukesh Kumar Suman: A comparative study of ballistic DG nMOS for 9.8nm gate length with Mixed gate oxide over single gate oxide by DC and RF analysis. (2013-2014)
  6. Suman Kr. Mitra: Optimization and Scaling of an SOI-TFET with Back Gate Control and Modelling of Drain Current. (2014-15)
  7. RahinPegu: Optimization and modelling of Electrical Characteristics of 3D Gate all around Silicon nano wire MOSFET with tri-material gate and comparison with conventional MOSFET (2014-15)
  8. Prasant Singh: Dual Metal Dual Dielectric SOI TFET with Gate Source overlap and Drain Underlap : simulation and Modelling (2015-16)
  9. KishanKumar : Optimization of Field plated High-K gate Dielectric AlGaN/GaN HEMTs for High Power Applications(2015-16)
  10. AtishKumar : Modelling and Simulation of AlGaN/GaN High Electron Mobility Transistors with pGaN CAP layer and AlGaN Buffer layer HEMT(2015-16)
  11. Dhrubajyoti Borah: Tunnel Field Effect Transistor on Selective Buried Oxide (SELBOX) Substrate (2016-17)
  12. Saurav Tiwari: Simulation of Graphene Nanowires Fet and comparison with different Nanowire structures (2016-17)
  13. V Puitea: Optimization of Electrical Parameters in Single Gate and Double Gate SiGe Channel nMOSFETs and their Application in Digital Inverter (2016-17)
  14. Vandana Devi: Optimization of Pocket doped Junctionless TFET and its Application in digital Inverter, 2017-2018
  15. Susmitha Kotha Palli: Optimization of Electrical Parameters of Gate Engineered Tunnel FET, 2018-2019
  16. Baishalee Sonowal : RADAR  software  integration in  RADAR based Auto SoC Verification (2019-2020)
  17. Urmila Bag: Simulation and reliability study of strained SOI TFET (2020-2021)
  18. Mayank Saini: Designing a Splittable IOMUX CELL used in Pin Multiplexing of the Automotive Microcontrollers” (2020-2021)
  19. Karra Venkata Lakshmi Sri ” Simulation and analysis of a Dual Source Vertical Tunnel Field Effect Transistor ( 2021-22)
  20. Samadrita Bhuiya “DESIGN AND OPTIMIZATION OF POLYGON-SHAPED-GATE OXIDE TFET FOR LOW-POWER APPLICATIONS” (2021-22)
  21. Nivedita, ” THROUGH-SILICON-VIA (TSV) INSERTION FOR AREA OPTIMIZATION OF SoC IN FOVEROS TECHNOLOGY” (2022-23)
  22. Maaz Ahmed “BLOCK LEVEL IMPLEMENTATION OF PHYSICAL DESIGN FLOW” (2022-23)
  23. TVS Kranti Kumar, “ CMOS 3 rd Order G m–C Lowpass Filter design for Electroencephalography, ” 2023-24
  24.  Ravi Kishan, ” Power-Optimized Dhrystone Benchmark Design for FPGA Boards, ” 2023-24

 Currently Guiding-1

1. Himjyoti Thakuria

B.Tech. Projects

  1. Pankaj , Amit Agarwala, Rohit Kr. Halder, Pragotipran Bora : FPGA BASED DPEM CONTROLLER for Low-Power DC-DC Converters (2009-2010)
  2. Anupaldeka, BiswrupNath, Mohit Dave, Shreya Dalela : design and Analysis of Fuzzy Logic based PID controller for PWM based Switching converter(2014-15)
  3. Rupesh Kumar Bhadu, Ramswarup Choudhury, rajesh Kumar Meena, SushmitaSaha : Germanium Source Silicon-On Insulator Tunnel Field Effect Transistors(2014-15)
  4. Ajeet Kumar, Anoop Sharma, Ashish Kumar PK, Bibhash Pathak, Saurabh Kumar Mangalam : Design of High Speed Low Power Comparator (2015-16)
  5. Aditya Kumar, Anuj Shukla, Tejpratap Singh, AkashAnupam : Optimization and Modelling of Elevated Source Drain TFET Structure (2014-15)
  6. Abhishek Mukherjee, DikshaBoruah, Medhavi, ShailendraSahu: Performance Analysis of Small Signal Amplifiers in Darlington andSziklai Configurations (2016-17)
  7. Parinita Biswas, AbhishekChakraborty : AIR Pollution Detection System Sychronised and Monitored in Cloud ( 2016-2017)
  8. ChandanJoishi, Maya Ramesh, Premraj Kumar, ParthaBaruah : 3D Analysis of Hetero Double Gate Tunnel Field Effect Transistor ( (2011-12)
  9. Arvind Kumar Singh, IndubhshanYadav, Mohit Kumar, Satyendra Narayan Mazumder: Optimization of Group III/V material based SOI MOSFET( 2012-13)
  10. AngshumanMadhab Dutta, Deepjyoti Sarkar, Rakesh Das, Jeetendra Prakash Sonkar: Electrical Charcteristics of Double gate FINFET ( 2015-16)
  11. Rajarshi Biswas, SantanuKar, Anil Kr Gautam, S Venkatesh: Vector Median Filtering of Colour images ( 2008-2009)
  12. PritamDey, Smith Ghosh, sanjeebKro, DeepjyotiKalita: Implementation of VIerbi Decoder using FPGA ( (2013-14)
  13. AnishNath, AbhisekBezbaruah, HeerokJyotiHazarika, ArunjyotiMusahary: MOSFET Simulation study (2013-14)
  14. Rajneesh Kumar, Roshan Kumar, K.Tenzing Singh, Swarnandu Das. Y. Ravindra Raj Singh: Efficient Design of PID controller implementing FPGA by using Xilinx (2010-11)
  15. Tushar Dutta, Akshitgarg, Rajnish Kumar, NitinRanawat: Speed Measurement and Control of DC Motor using Microprocessor (2009-10)
  16. Ayush Prakash: ” The missing link prediction problem ‘ 2018-2019
  17. Nirupam Das, ” COMPUTER NETWORKING AND ITS SECURITY ASPECTS” 2018-2019
  18. Arnab Das, Shreya Das, ” Analytical Model for Parasitic Fringe Capacitance in Gate Underlap Strained Silicon DG-MOSFET, 2020-2021
  19. Rahul Raj, Tanmay Kumar, ” Using NLP and Deep learning to give recommendation to user based on product’s text desription and of its image during online shopping, 2020-21
  20. Partha Pratim Goswami,” Optimization of pocket doped High K gate TFET with back gate” 2018-2019
  21. Chinmay Deka, Basabee Borah,” Optimization of Tunnel FET performance using Heterostructure ” 2019-2020
  22. KARASUDULA ANIRUDH, SAVLAPURAPU BHARAT, SMART HOME SYSTEM SENSITIVE DATA PRIVACY PRESERVING,2019-2020
  23.  Arshita Narayan, Suramya Das, Ruttala R, Dipesh Roy Choudhury’ “IoT based Soil Monitoring, Crop Prediction with Data Visualization and Data Collection for Tea Plantation” (2021-2022)
  24. Hrishikesh Borah ” Simulation and Study of Ferro electric FET” (2021-2022)
  25. Surajeet Barman and group, “Implementation of virtual Mouse and hand gesture detection” ( 2022-23)
  26. Aaryan, Abhigyan Dandrial, “IDENTIFYING AND OPTIMISING THE MISSING COMPONENTS IN A VLSI CIRCUIT USING ARTIFICIAL INTELLIGENCE,” 2023-24
  27. Satyam, Prithiviraj, Kavya, “DESIGN AND OPTIMISATION OF CLASS-D AUDIO AMPLIFIER,” 2023-24 

Current BTech project: 1. Aman Goala and Gr

2. Jhumur Santra and Gr

 

 

 

 

Workshops Organized

  1. One week workshop on Emerging Devices, Circuits and Systems(EDCS 2019), TEQIP and IEEE EDS, NIT Silchar, Silchar, 21- 25 Jan 2019, Convener.
  2. 3 days workshop on Workshop on Emerging devices, NIT Silchar, Sichar, TEQIP, October 2016, Coordinator
  3. 3 days workshop on Recent trends in Embedded System and its application,NIT Silchar, Silchar, Sept 2012, Coordinator
  4. One day workshop on Sexual Harassment of women at work place, NIT Silchar, Silchar, Institute Fund, Oct 2015, organized on behalf of ICC NIT Silchar