Dr. KAVICHARAN MUMMANENI

March 16, 2022 by M Kavicharan
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                                                                                                                                                                                  kavicharan photo

Assistant Professor-I

National Institute of Technology (NIT) Silchar

Department of Electronics and Communications Engineering

Silchar, Assam, 788010, India

Email: kavicharan@ece.nits.ac.in

Phone: +91-8919656541

Date of Joining: 15/06/2018

Academic Experience: 9+ years

Personal Webpage: http://ec.nits.ac.in/kavicharan/

ACADEMIC QUALIFICATIONS

  • Ph.D.:     NIT Warangal, Warangal, India, 2015
  • M.Tech.: NIT Calicut, Calicut, India, 2009
  • B.Tech.: JNTU Hyderabad, Hyderabad, India, 2006

EXPERIENCE

  • June 2018 – Till date: Assistant Professor, National Institute of Technology (NIT) Silchar, Assam, 788010, India
  • July 2017 – June 2018: Assistant Professor, Thapar University, Patiala, Punjab, India.
  • Jan. 2015-June 2017: Assistant Professor, MREC, Hyderabad, India.
  • July 2009-May 2010, Assistant Professor, SDES, Hyderabad, India.

RESEARCH INTERESTS AND SPECIALIZATION

VLSI interconnects, Micro and nanoelectronic devices, Digital Circuits, FPGA-based designs, Embedded systems, Carbon Nanotube Interconnects, Stretchable interconnects, Machine learning for VLSI Physical design

BIOGRAPHICAL SKETCH

Dr. Kavicharan was born in Telangana, India, in 1985. He obtained his Bachelor of Technology from JNTU Hyderabad in 2006. He obtained his Master of Technology from NIT Calicut in 2009 and Ph.D. from NIT Warangal in 2015. He is having teaching and research experience more than 8 years in various organizations.

He joined the National Institute of Technology (NIT), Silchar on 15th June 2018. He is a Senior Member of IEEE. His research interests are VLSI interconnects, Micro and nanoelectronic devices, Digital Circuits, FPGA-based designs, Embedded systems, Carbon Nanotube Interconnects, Stretchable interconnects, Machine learning for VLSI Physical design

PUBLICATIONS (JOURNALS/CONFERENCES)

International Journals

  1. Dubey, D. K. Jarwal, H. Kumar, Y. Kumar, K. Mummaneni and G. Rawat, “Development of Highly Efficient ZnO Nanorod-Based Nontoxic Perovskite Solar Cell Using AZO Buffer Layer and Lanthanide Doping,” in IEEE Transactions on Electron Devices, vol. 69, no. 2, pp. 622-630, Feb. 2022, doi: 10.1109/TED.2021.3138375.
  2. Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni, “Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric Tunnel FET”, Materials Science in Semiconductor Processing, Volume 142, 2022, 106482, ISSN 1369-8001, https://doi.org/10.1016/j.mssp.2022.106482.
  3. Malvika, Bijit Choudhuri, Kavicharan Mummaneni, “A Review on a Negative Capacitance Field Effect Transistor for Low Power Applications” Journal of Electronic Materials (2022), DOI: 10.1007/s11664-021-09384-8.
  4. Sharma, S. Kumar, J. Talukdar, K. Mummaneni, G. Rawat, “Source Pocket-Engineered Hetero-Gate Dielectric SOI Tunnel FET with Improved Performance”, Materials Science in Semiconductor Processing, 2022, (Accepted for publication)
  5. Jagritee Talukdar, Gopal Rawat, Kavicharan Mummaneni, “Noise behaviour and Reliability Analysis of Non-Uniform Body Tunnel FET with Dual Material Source” Microelectronics Reliability, 2022, (Accepted for publication)
  6. Jagritee Talukdar & Kavicharan Mummaneni, A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature, Silicon, 2021 Doi: 10.1007%2Fs12633-021-01224-y.
  7. Talukdar, G. Rawat and K. Mummaneni, “Dielectrically Modulated Single and Double Gate Tunnel FET based Biosensors for Enhanced Sensitivity,” IEEE Sensors Journal, 2021, doi: 10.1109/JSEN.2021.3122582.
  8. Talukdar, G. Rawat K. Mummaneni, A Novel Extended Source TFET with δp+- SiGe Layer, Silicon, 12:2273–2281, (2019) doi: 10.1007/s12633-019-00321-3.
  9. Talukdar, K. Mummaneni, A non‑uniform silicon TFET design with dual‑material source and compressed drain, Applied Physics A, 126, (81) (2020) DOI: https://doi.org/10.1007/s00339-019-3266-5.
  10. Talukdar, G. Rawat, K.Singh, K. Mummaneni, Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with dp+ SiGe Pocket Layer, Journal of Electronic Materials, 49(7), (2020), 4333-4342.
  11. Talukdar,  G. Rawat,  K. Singh, K. Mummaneni, Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET, Silicon (2020), https://doi.org/10.1007/s12633-020-00712-x.
  12. Talukdar, G. Rawat, K.Singh, B. Choudhury, K. Mummaneni, Device Physics Based Analytical Modeling for Electrical Characteristics of Single Gate Extended Source Tunnel FET(SG-ESTFET), Superlattices and Microstructures, Volume 148, December 2020, 106725
  13. Talukdar, J., Choudhuri, B. & Mummaneni, K. Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer, Applied. Physics. A 127, 24 (2021).
  14. Kavicharan, N.S.Murthy and N.Bheema Rao “Efficient delay and crosstalk estimation models for current-mode high speed interconnects under ramp input,” Journal of circuits, systems, and computers, World scientific publishers, Vol. 23, Issue 6, July 2014.
  15. S.Murthy, M.Kavicharan “A survey on Finite difference time domain method for interconnect analysis,” Journal of circuits, systems, and computers, World scientific publishers Vol. 24, Issue 1, Jan 2015.
  16. Kavicharan, N.S.Murthy and N.Bheema Rao “Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects,” Springer Circuits, Systems and Signal Processing, vol. 34, Issue 12, Dec 2015.
  17. Kavicharan, N.S.Murthy and N.Bheema Rao “Transient Analysis of VLSI Tree Interconnectsbased on Matrix Pade Type Approximation” The WSEAS Transactions on Circuits and Systems pp. 360-367, Vol. 13, 2014.

International Conferences

  1. Abhishek Zade, Sumit Kumar Singha, Jagritee Talukdar, Addanki Prathima, Kavicharan Mummaneni, “Implementation of Arithmetic Logic Unit using Area Efficient Adder” International Conference on Computational Intelligence & Sustainable Technologies (ICoCIST-2021), NIT Sikkim.
  2. Pragya Pandey, Kajal Kumari, Malvika, Addanki Prathima, Kavicharan Mummaneni, “Optimized design of ALU using Reversible Gate” International Conference on Computational Intelligence & Sustainable Technologies (ICoCIST-2021), NIT Sikkim (Accepted).
  3. Talukdar and K. Mummaneni, “Impact of temperature and different types of trap charges on noise behavior of Non-uniform Body with Dual Material Source TFET (NUTFET-DMS),” 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 541-544, doi: 10.1109/DevIC50843.2021.9455914.
  4. Talukdar and K. Mummaneni, “Noise Behavior of SG-ESTFET with Various Interface Trap Charges,” 2020 International Conference on Computational Performance Evaluation (ComPE), Shillong, India, 2020, pp. 222-225, doi: 10.1109/ComPE49325.2020.9200121.
  5. Ganaraj P S, Dr. Koushik Guha, Dr. Kavicharan M, Design of SIW based filter for Ka Band, IEEE (EDS), Micro2020: 7th International Conference on Microelectronics, Circuits & Systems, Delhi Technological University, Delhi, 5th-26th July 2020.
  6. Hariprasad Ganji, Ravindra Kumar Maurya, Kavicharan Mummaneni, Design of High-Speed 32-Bit Vedic Multiplier Using Verilog HDL, International conference on micro/nanoelectronics Devices, Circuits and Systems, NIT Silchar, 29-31 January 2021.
  7. Makumsibou R Zeliang, Malvika and Kavicharan Mummaneni, Efficient Full Adder Design based on New Reversible Tuned Fredkin Gate (TFG), International conference on micro/nanoelectronics Devices, Circuits and Systems, NIT Silchar, 29-31 January 2021.
  8. Shashikumar M, Bhaskar Jyoti Das,Jagritee Talukdar, Kavicharan Mummaneni, Radix-10 Multiplier Implementation with Carry skip adder using Verilog, International conference on micro/nanoelectronics Devices, Circuits and Systems, NIT Silchar, 29-31 January 2021.
  9. Jagritee Talukdar, G. Amarnath, Kavicharan Mummaneni, Flicker noise analysis of Non-uniform body TFET with dual material source (NUTFET-DMS), International conference on micro/nanoelectronics Devices, Circuits and Systems, NIT Silchar, 29-31 January 2021.
  10. Amarnath, Manisha Guduri, Vinod A, M. Kavicharan, Study of Temperature Effect on MOS-HEMT Small-Signal Parameters, International conference on micro/nanoelectronics Devices, Circuits and Systems, NIT Silchar, 29-31 January 2021.
  11. Dhritishman Sarmah, Vivek Kumar, M. Kavicharan “Analytical Modeling of Delay and Overshoot in High-Speed VLSI Interconnects” International Conference in Recent Trends on Electronics & Computer Science (ICRTECS-2019) 18th- 19th March 2019.
  12. Krishna Mohan, Aryan Sarthi, M. Kavicharan, “Matrix Pade-Type-Routh model Reduction based Delay model for VLSI Interconnects”, International Conference in Recent Trends on Electronics & Computer Science (ICRTECS-2019) 18th- 19th March 2019
  13. Kavicharan, N.S.Murthy and N. Bheema Rao “Modal Decomposition-based VLSI Interconnect Delay Modeling,” Proceedings of  International Conference on Solid-State and Integrated Circuit (ICSIC 2012), Singapore, vol.32 (2012) pp 23-27.
  14. Kavicharan, M.; Murthy, N.S.; Rao, N.B., “A closed-form delay estimation model for current-mode high speed VLSI interconnects,” International Conference on  Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE), IEEE, held at Konya, Turkey, pp.502-506, 9-11 May 2013.
  15. Kavicharan, M.; Murthy, N.S.; Rao, N.B., “An efficient delay estimation model for high speed VLSI interconnects,” International Conference on  Advances in Computing, Communications and Informatics (ICACCI), IEEE, held at Mysore, pp.1358-1362, 22-25 Aug. 2013.
  16. Kavicharan, N.S.Murthy and N.Bheema Rao “An Efficient Distributed Tree Structure Modelling for VLSI circuits,” Proceedings of the 2014 International Conference on Circuits, Systems, Signal Processing, Communications and Computers (CSSCC ’14), held at Venice, Italy, pp. 61-65, March 15-17, 2014.
  17. Kavicharan, N.S.Murthy and N.Bheema Rao “A Novel Delay and Overshoot Estimation model for VLSI Global Interconnects,” 18th international Conference on Circuits, Systems, Communications and Computers, held at Greece, pp. 272-276, 17-21 July, 2014.
  18. Kavicharan, N.S.Murthy and N.Bheema Rao “A novel hybrid signalling scheme for VLSI global Interconnects,” 18th international Conference on Circuits, Systems, Communications and Computers, held at Greece, pp. 251-256, 17-21 July, 2014.

BOOKS/CHAPTERS

  1. Ganaraj P.S., Guha K., Kavicharan M. (2022) Substrate Integrated Waveguide (SIW)-Based Filter for Ka Band Applications. In: Chanda C.K., Szymanski J.R., Sikander A., Mondal P.K., Acharjee D. (eds) Advanced Energy and Control Systems. Lecture Notes in Electrical Engineering, vol 820. Springer, Singapore. https://doi.org/10.1007/978-981-16-7274-3_21.
  1. Malvika, Bijit Choudhuri and Kavicharan Mummaneni, Performance analysis of MFIS NCFET for various channel material, Micro/Nanoelectronics Devices, Circuits, and Systems, Lecture Notes in Electrical Engineering, vol 781, Springer, Singapore 2022.
  2. Anusmita Kakati, Ganaraj Shankar, Koushik Guha and M Kavicharan, “Design and Analysis of MEMS Varactor for Ka Band Applications” Micro/Nanoelectronics Devices, Circuits, and Systems, Lecture Notes in Electrical Engineering, vol 781, Springer, Singapore 2022.
  3. Jagritee Talukdar, Pankaj Saksena and Kavicharan Mummaneni, “Design and Analysis of Non-Uniform Body with Dual Material FET based Digital Inverter” Micro/Nanoelectronics Devices, Circuits, and Systems, Lecture Notes in Electrical Engineering, vol 781, Springer, Singapore 2022.
  4. Pulumati Chidananda, Chappa Vinay Kumar, Rajan Singh and Mummaneni Kavicharan, “Optimized RTL design of a vending machine through FSM using Verilog HDL” Micro/Nanoelectronics Devices, Circuits, and Systems, Lecture Notes in Electrical Engineering, vol 781, Springer, Singapore 2022.

PROFESSIONAL MEMBERSHIPS

  • Senior Member, IEEE
  • IEEE Electron Device Society, Member
  • IEEE Circuits and Systems Society, Member
  • Member, IEEE Nanotechnology Council

ADMINISTRATIVE RESPONSIBILITIES

  • DPPC Secretary, ECE Dept., NIT Silchar
  • Program Coordinator of M.Tech ME&VLSID, ECE Dept., NIT Silchar
  • March 2022 to till date: DPPC Secretary, ECE Department, NIT Silchar.
  • Associate Lab in charge of Computational Lab, ECE Dept., NIT Silchar
  • Quality Assurance and Control Committee (QACC) – Co-Coordinator
  • Faculty mentor B.Tech. 2nd Year Students

Ph.D. Scholars

Full-time

1.     Jagritee Talukdar (Completed) 

2.     Malvika [2019] (Ongoing) 

3.      Vivek Kumar [2021] (Ongoing)

M.Tech. Projects

1.      Customized Routing Algorithm for Timing Collateral on Layout Tool
2.      Efficient delay and crosstalk estimation models of CNT interconnects
3.      Machine learning based reduced-order modeling of VLSI interconnects4.        Delay analysis of different stretchable interconnect structures

B.Tech. Projects

  1. Design and Optimization of Solar cell Parameters for Enhanced Photovoltaic Performance
  2. Design and modelling of flow kinetics in proximal tubule for Kidney-on-chip applications
  3. Deep Neural Network based Approach for ECG Signal Classification
  4. Utilisation of Machine learning for Prediction of diseases based on symptoms
  5. Modelling of Carbon Nanotube VLSI Interconnects
  6. Performance analysis of On-chip interconnects using neural networks
  7. Machine Learning for the Performance Assessment of High-Speed Links

Workshops Organized

  1. “Prototype/Process Design and Development”  organized by the IIC 4.o in association with the Department of Electronics and Communication Engineering & Department of Management Studies, NIT Silchar, 14th to 18th February 2022, Coordinator
  2. “Recent Trends in Innovative CMOS-MEMS Technologies and Applications: Hands on Learning”, TEQIP-III Sponsored, Dept. of ECE, NIT Silchar, Silchar, 11/09/2020 to 15/09/2020, Coordinator.
  3. “Modeling of Novel Nano electronic Devices and Circuits for ULSI Technology”, DST-SERB and TEQIP-III sponsored, Dept. of ECE, NIT Silchar, Silchar, 26/04/2019 to 30/04/2019, Coordinator
  4. “Emerging trends in Analog and Digital design using Cadence: Hands on Learning”, MREC, Hyderabad, 06/06/2016 to 11/06/2016, Coordinator